FCDEV3B update

[Mychaela Falconia]

Hello FreeCalypso community,

It's time for another update on where things stand.  The order for the
PCB fabrication that has been paid for in early January is still on
hold as of this moment, but I am hoping that it will finally get
released from hold in another couple of days or maybe even later
today.

Regarding the layer stackup and prepreg materials, reproducing the
exact stackup used by FIC/Openmoko for the GTA02 a decade ago appears
to be impossible: the combination of glass type 1078 in ordinary FR4
epoxy resin (as opposed to some fancy advanced resin system with a
totally different dielectric constant) is simply no longer made.  In
order to rule out the possibility of pcbcart being not diligent
enough, I have talked to some other fabs including Advanced Circuits
in Colorado (USA-occupied Incalia), and their senior guy who called me
after I couldn't get anywhere with the sales rep explained to me that
the current industry thinking is that putting an advanced glass fabric
into plain FR4 epoxy resin "is like putting a Lambourghini engine into
a Ford", hence no one makes such combination.

Naturally this explanation raises the question of why FIC used PP 1078
for their outer dielectric layers back in 2008.  The closest I came to
a potentially plausible answer is that perhaps they did what they did
not because of special electrical properties of their PP 1078, but for
manufacturing process reasons, having to do with the laser microvias
which have to be drilled through these same outer layers.

Let's review the drill structure of the GTA02 motherboard (necessarily
copied for our FCDEV3B) once more.  There are 8 copper layers in total,
with 7 dielectric layers in between, and the via drill structure goes
as follows: L1-L2, L2-L3, L3-L6, L6-L7, L7-L8.  This drill structure
can only be produced by way of multiple press cycles and controlled
depth laser drilling as follows:

Step 1: The L4-L5 core and the L3-L4 and L5-L6 prepregs are pressed
together (the combination of heat and pressure cures and solidifies
the prepreg), forming the L3-L6 inner core of the board, and this
L3-L6 is drilled (regular mechanical drills can be used) to produce
the inner L3-L6 buried vias.

Step 2: L2-L3 and L6-L7 prepregs are pressed onto the L3-L6 core, and
then the L2-L3 and L6-L7 microvias have to be produced by controlled
depth drilling with a laser.  It is not possible to form these vias by
drilling through a layer of prepreg separately before pressing the PP
onto the core, hence one has to do controlled depth drilling after the
press cycle that solidifies the PP.  Because of the controlled drill
depth requirement and the tiny size of these microvias (4 mils or
0.10 mm diameter), laser drilling must be employed.

Step 3: L1-L2 and L7-L8 prepregs are pressed onto the L2-L7 core
resulting from steps 1 and 2, and the L1-L2 and L7-L8 microvias are
produced by the same process as in step 2.

As I learned recently, the process of controlled depth laser drilling
to produce microvias involves its own host of challenges, and has been
evolving over the years.  At one time they didn't even use
glass-reinforced prepreg at all for dielectric layers with microvias
going through them, but rather used resin-coated copper (RCC), i.e.,
the dielectric was resin with no glass reinforcement in it.  Then they
came up with what was (or still is?) called laser-drillable prepreg or
LDP - thus apparently it had (and maybe still has) to be a special
kind of prepreg to be suitable for laser drilling of microvias.

Given the discoveries above, I wonder if perhaps FIC used PP 1078
instead of 1080 for the outer dielectric layers because the thinner
prepreg was easier for them to drill through, or maybe some property
of 1078 glass worked better for their laser drilling process.  But
today's fabs including pcbcart (the fab we are working with for our
FCDEV3B) apparently have no difficulty with laser-drilling microvias
through regular PP 1080, hence they now use the latter in their
standard stackups.

Once I learned all of the above, I emailed pcbcart and told them that
it's OK to alter the stackup by changing PP 1078 to 1080, adjusting
other dielectric thicknesses accordingly, and adjusting the RF trace
widths to maintain 50 ohm impedance.  I told them that our RF circuits
need to operate in the frequency range from 824 to 1990 MHz (the
superset of the UL and DL ranges for all 4 GSM bands), there was a bit
of a concern that the materials they selected initially may not
perform well in this frequency range, and then they wrote:

> Good news, our engineer suggest change the material to "IT-180A", it is
> our highest productive line, it can reach your frequency required.

With this change of material they proposed a new stackup, which I
posted here:

https://www.freecalypso.org/members/falcon/fcdev3b/pcbcart/

stackup-20170215.xls is the proprietary Micro$oft XLS file they sent
me; stackup-20170215.txt and stackup-20170215.png are the content
extracts from it.  The XLS has some conventional row/column content in
it as well as an embedded bitmap picture; the TXT file contains the
former and the PNG contains the latter.  The PNG picture that was
originally embedded in the XLS is the layer stackup drawing, while the
row/column data I saved in plain text format gives the trace width
adjustments for 50 ohm controlled impedance.

This new stackup is actually better than pcbcart's previous proposal
in that there is less adjustment to the trace widths:

* L8 microstrips: 11 mil in Openmoko's original, pcbcart's first
  proposal increased them to 12.8 mil, with the current stackup
  they'll be 11.8 mil.

* L5 striplines: 6.95 mil in Openmoko's original, pcbcart's first
  proposal shrunk them to 5.15 mil, with the current stackup they will
  be 6.3 mil.

Widening the RF traces on L8 beyond the original design creates a risk
of undesirable coupling to other nearby traces, whereas shrinking the
Tx path traces on L5 reduces their current carrying capacity.  Pcbcart's
initial proposal of widening L8 to 12.8 mil while shrinking L5 to
5.15 mil made me feel uneasy, but with their current proposal the
trace widths are close enough to Om's original that I don't expect any
problems.  Oh, and the copper weight remains 1 oz on all layers like
in Om's original.

With the stackup issue finally brought to an agreement, there is now
only one issue that needs to be resolved before our PCB fabrication
order can be released from hold.  Our board is fairly small, only
90x50 mm, and small boards like ours are typically panelized: the
delivery from the PCB fabricator to the assembly house takes the form
of panels instead of fully cut individual PCBs, with each panel
containing several copies of the individual PCB, to be cut out after
the SMT reflow assembly step, i.e., after most of the components are
populated.

Pcbcart have proposed a particular panelization for our boards, and
now I need to get this panelization reviewed and approved by the
assembly shop I'm going to use.  I am hoping to hear from them later
today.

If we get the PCB fab order released from hold in the next few days,
we should have the boards back around the end of March.  Then we'll be
ready to go into assembly.  I already have all of the needed parts on
hand, but one of the BGAs (the Spansion flash+pSRAM memory IC) still
needs to be reballed from RoHS to SnPb.  I got back in touch with the
company from which I got the BGA reballing price quote back in April
of 2016, and they said that price is still good.  I will be sending
them 20 of our Spansion BGA chips for the reballing, and hopefully
they will come back with SnPb solder balls at around the same time as
the PCBs.  Thus if everything goes well, the moment of truth (do our
boards work?) will come in early April.

Hasta la Victoria, Siempre,
Mychaela aka The Mother