The only difference between FCDEV3B V1 and V2 boards is the connection of the
flash reset input, i.e., U301 ball D5.  On FCDEV3B V1 this flash reset input is
connected to the FDP output from the Calypso (U201 ball F4), whereas on V2 this
flash reset input is sourced from the newly added buffer IC at reference
designator U303, as detailed in the FCDEV3B V2 schematic source code and 
explanatory notes released in the fcdev3b-v2-nongraph-schem.tar.gz package.
This change allows the use of S71PL129N flash without causing flash reset timing
problems; the use of the same flash chip on V1 boards without the reset circuit
change was the cause of the sleep mode bug that manifests on those old boards.
There are no other differences.