ECO 1 for OSDCU PCB rev 0

Background information

If the OSDCU is used in the Layer 2 protocol converter mode (EIA-530 link
decoupled from the actual SDSL bit stream), the hardware design allows a
different clock to be used on the EIA-530 side that is essentially independent
of BCLK.  The primary motivation is to allow the OSDCU to host direction to be
clocked at a higher rate so that no Rx packets can ever get dropped regardless
of how the ATM->HDLC conversion works out.

The approach for generating this independent fast clock that has made its way
into PCB rev 0 uses a 74HCT74 divider to produce 2xBCLK from the bitpump's HCLK
output.  On deeper thought however, this approach has been found to be very
suboptimal for at least two reasons:

* Modeling shows that HDLC is generally more bit-efficient than ATM.  Although
  it *is* possible to have packets on a network which would require more bits
  in the HDLC representation than in the ATM representation, such packets are
  expected to be very rare, and the number of "extra" bits needed on the HDLC
  side is very small.  Therefore, it may still be desirable to run the HDLC
  link at a slightly higher rate, but doubling seems to be extreme overkill.
  Given that all WAN interfaces have some limits on the maximum clock rates
  they can handle, that overkill is also deemed anti-social.

* There is an unused clock generator in the OSDCU design.  Each MC68302 SCC has
  a BRG, and if the SCC uses external clocks, the associated BRG can be
  appropriated for other unrelated uses.  In our design BRG3 is used to generate
  asynchronous serial baud rates for SCC3, BRG2 is unused but its output is not
  available (pin multiplexing), but BRG1 is unused and its output is available
  on a dedicated output pin.

Change description

This ECO calls for 2xBCLK to be replaced with the BRG1 output.  This change is
deemed to be an improvement by every measure:

* A part (74HCT74 divider IC at U20) is eliminated from the BOM.  Because it is
  the only component of this type in the design, it eliminates an entire BOM
  position rather than just save one part on the quantity.

* BRG1 can be programmed to generate any desired clock rate in fairly fine-
  grained increments, not just double BCLK.

The only loss with this ECO is that the software clock can no longer be set to
*exactly* the double of BCLK, although if someone desires a clock rate in that
vicinity, it can be set rather close.  This feature loss is not deemed to be a
problem: aside from any judgment on whether or not a clock of approximately
2xBCLK is desirable, there obviously exists no need for it to be exactly 2xBCLK.

ECO instructions

1. Omit components U20, C34 (bypass cap for U20) and R31 (HCLK series resistor)
   from the board population.

2. Run a board rework wire from U1 pin 76 (MC68302 output BRG1) to the
   unpopulated pad for U20 pin 9.  This wire will feed BRG1 to the PCB
   trace where 2xBCLK used to be.

3. If fast signal series resistor R32 was omitted from the board population,
   populate it now.  Its "input" side is wired to U20 pin 9 where BRG1 goes now,
   and its "output" side goes to MUXes U14 and U15.

Future plans

The next PCB revision will incorporate this ECO.