fc-magnetite: src/cs/layer1/tpu_drivers/source0/tpudrv12.h annotate

annotate src/cs/layer1/tpu_drivers/source0/tpudrv12.h @ 639:026c98f757a6

tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only As it turns out, there exist two different Huawei-made hw platforms both bearing the marketing name GTM900-B: one is MG01GSMT, the other is MGC2GSMT. The two are NOT fw-compatible: aside from flash chip differences which should be handled by autodetection, the two hw platforms are already known to have different RFFEs with different control signals, and there may be other differences not yet known. Our current gtm900 build target is for MGC2GSMT only; we do not yet have a specimen of MG01GSMT on hand, hence no support for that version will be possible until and unless someone provides one.

author	Mychaela Falconia <falcon@freecalypso.org>
date	Thu, 30 Jan 2020 18:19:01 +0000
parents	d968a3216ba0
children	3fb7384e820d

rev	line source
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /**************** Revision Controle System Header *********************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 * GSM Layer 1 software
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 * Copyright (c) Texas Instruments 1998
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * Filename tpudrv12.h
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 * Copyright 2003 (C) Texas Instruments
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 **************** Revision Controle System Header *********************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 //--- Configuration values
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 #define FEM_TEST 0 // 1 => ENABLE the FEM_TEST mode
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12 #define RF_VERSION 1 // 1 or V1, 5 for V5, etc
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 #define SAFE_INIT_WA 0 // 1 => ENABLE the "RITA safe init"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 // TeST - Enable Main VCO buffer for test
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 #define MAIN_VCO_ACCESS_WA 0 // 1 => ENABLE the Main VCO buffer
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 #include "rf.cfg"
602 92dbfa906f66 fc-target.cfg config header renamed to more sensible fc-target.h Mychaela Falconia <falcon@freecalypso.org> parents: 600 diff changeset	18 #include "fc-target.h"
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 //--- RITA PG declaration
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 #define R_PG_10 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 #define R_PG_13 1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 #define R_PG_20 2 // For RFPG 2.2, use 2.0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 #define R_PG_23 3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 //--- PA declaration
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28 #define PA_MGF9009 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 #define PA_RF3146 1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 #define PA_RF3133 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 #define PA_PF08123B 3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 #define PA_AWT6108 4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34 #if (RF_PA == PA_MGF9009 \|\| RF_PA == PA_PF08123B)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 #define PA_CTRL_INT 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 #define PA_CTRL_INT 1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40 //- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 // AlphaRF7 => "PG #1.3" for TPU purposes (not an official PC number)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 // This is also used in l1_rf12.h to select the SWAP_IQ
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43 #if (RF_PG >= R_PG_20)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 #define PLL2_WA 0 // 0 => DISABLE the PLL2_WA (Rene's "Work-Around")
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #define ALPHA_RF7_WA 0 // 0 => DISABLE the Alpha RF7 work-arounds
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #elif (RF_PG == R_PG_13)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 //- Bit definitions for TST register programings, etc
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 #define BIT_0 0x000001
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 #define BIT_1 0x000002
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60 #define BIT_2 0x000004
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #define BIT_3 0x000008
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #define BIT_4 0x000010
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #define BIT_5 0x000020
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 #define BIT_6 0x000040
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 #define BIT_7 0x000080
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 #define BIT_8 0x000100
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 #define BIT_9 0x000200
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 #define BIT_10 0x000400
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 #define BIT_11 0x000800
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70 #define BIT_12 0x001000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 #define BIT_13 0x002000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 #define BIT_14 0x004000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 #define BIT_15 0x008000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 #define BIT_16 0x010000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 #define BIT_17 0x020000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 #define BIT_18 0x040000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 #define BIT_19 0x080000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78 #define BIT_20 0x100000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79 #define BIT_21 0x200000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 #define BIT_22 0x400000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 #define BIT_23 0x800000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 //--- TRF6151 definitions ------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 //- BASE REGISTER definitions
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 #define REG_RX 0x000000 // MODE0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 #define REG_PLL 0x000001 // MODE1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88 #define REG_PWR 0x000002 // MODE2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #define REG_CFG 0x000003 // MODE3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 //- TeST REGISTER definitions => Used for WA only
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92 // TeST - PLL2 WA => Define PLL2 TEST register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 #define TST_PLL2 0x00001E // MODE 14
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 // TeST - Enable Main VCO buffer for test => Define TST_VCO3 register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96 #define TST_VCO3 0x00000F // MODE 15 (016+151)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97 #define TST_VCO4 0x000024 // MODE 36 (216+41)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 // Alpha RF7 WA TeST registers
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 #define TST_LDO 0x000027 // MODE 39 (216+71)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 #define TST_PLL1 0x00001D // MODE 29 (116+131)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102 #define TST_TX2 0x000037 // MODE 55 (316+71)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 // More Alpha RF7 WA TeST registers
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105 #define TST_TX3 0x00003C // MODE 61 (316+121)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 #define TST_TX4 0x00003D // MODE 61 (316+131)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108 // PG 2.1 WA TeST registers
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109 #define TST_PLL3 0x00001F // MODE 31 (116+151)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 // #define TST_PLL4 0x00002C // MODE 44 (216+121)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 #define TST_MISC 0x00003E // MODE 62 (316+141) => Used for setting the VCXO current
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112 #define TST_LO 0x00001C // MODE 28 (116+121)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114 // Registers used to improve the Modulation Spectrum in DCS/PCS for PG2.1 V1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 // UPDATE_SERIAL_REGISTER_COPY is a "dummy addres" that,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 // when accessed, triggers the copy of the serial registers.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 // This is necessary to switch into "manual operation mode"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 #define UPDATE_SERIAL_INTERFACE_COPY 0x000007
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119 #define TX_LOOP_MANUAL BIT_3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 //- REG_RX - MODE0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 #define BLOCK_DETECT_0 BIT_3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124 #define BLOCK_DETECT_1 BIT_4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 #define RST_BLOCK_DETECT_0 BIT_5
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 #define RST_BLOCK_DETECT_1 BIT_6
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127 #define READ_EN BIT_7
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128 #define RX_CAL_MODE BIT_8
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 #define RF_GAIN (BIT_10 \| BIT_9)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 //- REG_PLL - MODE1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133 //PLL_REGB
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134 //PLL_REGA
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136 //- REG_PWR - MODE2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 #define BANDGAP_MODE_OFF 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 #define BANDGAP_MODE_ON_ENA BIT_4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 #define BANDGAP_MODE_ON_DIS (BIT_4 \| BIT_3)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 #define REGUL_MODE_ON BIT_5
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141 // BIT[8..6] band
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 #define BAND_SELECT_GSM BIT_6
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 #define BAND_SELECT_DCS BIT_7
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 #define BAND_SELECT_850_LO BIT_8
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145 #define BAND_SELECT_850_HI (BIT_8 \| BIT_6)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146 #define BAND_SELECT_PCS (BIT_8 \| BIT_7)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 #define SYNTHE_MODE_OFF 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149 #define SYNTHE_MODE_RX BIT_9
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 #define SYNTHE_MODE_TX BIT_10
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 #define RX_MODE_OFF 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152 #define RX_MODE_A BIT_11
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 #define RX_MODE_B1 BIT_12
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 #define RX_MODE_B2 (BIT_12 \| BIT_11)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155 #define TX_MODE_OFF 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156 #define TX_MODE_ON BIT_13
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 #define PACTRL_APC_OFF 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 #define PACTRL_APC_ON BIT_14
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159 #define PACTRL_APC_DIS 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 #define PACTRL_APC_ENA BIT_15
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 //- REG_CFG - MODE3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 // Common PA controller settings:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 #define PACTRL_TYPE_PWR 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 #define PACTRL_TYPE_CUR BIT_3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167 #define PACTRL_IDIOD_30_UA 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 #define PACTRL_IDIOD_300_UA BIT_4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170 // PA controller Clara-like (Power Sensing) settings:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 #define PACTRL_VHOME_610_MV (BIT_7 \| BIT_5)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172 #define PACTRL_VHOME_839_MV (BIT_7 \| BIT_5)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 #define PACTRL_VHOME_1000_MV (BIT_6 \| BIT_9)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174 #define PACTRL_VHOME_1600_MV (BIT_8 \| BIT_5)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 #define PACTRL_RES_OPEN 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176 #define PACTRL_RES_150_K BIT_10
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177 #define PACTRL_RES_300_K BIT_11
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 #define PACTRL_RES_NU (BIT_10 \| BIT_11)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 #define PACTRL_CAP_0_PF 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180 #define PACTRL_CAP_12_5_PF BIT_12
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 #define PACTRL_CAP_25_PF (BIT_13 \| BIT_12)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 #define PACTRL_CAP_50_PF BIT_13
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184 // PACTRL_CFG contains the configuration of the PACTRL that will
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185 // be put into the REG_CFG register at initialization time
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 // WARNING - Do not forget to set the PACTRL_TYPE (PWR or CUR)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 // in this #define!!!
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 #if (RF_PA == 0) // MGF9009 (LCPA)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 #define PACTRL_CFG \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190 PACTRL_IDIOD_300_UA \| \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 PACTRL_CAP_25_PF \| \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192 PACTRL_VHOME_1000_MV \| \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 PACTRL_RES_300_K
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 #elif (RF_PA == 1) // 3146
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 #define PACTRL_CFG 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197 #elif (RF_PA == 2) // 3133
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 #define PACTRL_CFG 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200 #elif (RF_PA == 3) // PF08123B
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 #define PACTRL_CFG \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202 PACTRL_TYPE_PWR \| \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203 PACTRL_CAP_50_PF \| \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 PACTRL_RES_300_K \| \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205 PACTRL_VHOME_610_MV
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 #elif (RF_PA == 4) // AWT6108
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 #define PACTRL_CFG 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 #error Unknown PA specifiec!
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212 // Temperature sensor
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 #define TEMP_SENSOR_OFF 0x0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214 #define TEMP_SENSOR_ON BIT_14
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 // Internal Logic Init Disable
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216 #define ILOGIC_INIT_DIS BIT_15
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217 // ILOGIC_INIT_DIS must be ALWAYS set when programming the REG_CFG register
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 // It was introduced in PG 1.2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 // For previous PGs this BIT was unused, so it can be safelly programmed
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 // for all PGs
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223 // RF signals connected to TSPACT [0..7]
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	224
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	225 #ifdef CONFIG_TARGET_PIRELLI
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	226 #define RF_RESET_LINE BIT_5
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	227 #else
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	228 #define RF_RESET_LINE BIT_0
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	229 #endif
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	230
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	231 #define RF_SER_ON RF_RESET_LINE
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 #define RF_SER_OFF 0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	234 #define TEST_TX_ON 0
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	235 #define TEST_RX_ON 0
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236
632 d968a3216ba0 new tangomdm build target Mychaela Falconia <falcon@freecalypso.org> parents: 608 diff changeset	237 #if defined(CONFIG_TARGET_LEONARDO) \|\| defined(CONFIG_TARGET_ESAMPLE) \|\| \
d968a3216ba0 new tangomdm build target Mychaela Falconia <falcon@freecalypso.org> parents: 608 diff changeset	238 defined(CONFIG_TARGET_TANGO)
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	240 // 4-band config (E-sample, P2, Leonardo)
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	241 #define FEM_7 BIT_2 // act2
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	242 #define FEM_8 BIT_1 // act1
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	243 #define FEM_9 BIT_4 // act4
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	245 #define PA_HI_BAND BIT_3 // act3
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	246 #define PA_LO_BAND 0
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	247 #define PA_OFF 0
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	249 #define FEM_PINS (FEM_7 \| FEM_8 \| FEM_9)
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	251 #define FEM_OFF ( FEM_PINS ^ 0 )
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	253 #define FEM_SLEEP ( 0 )
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 // This configuration is always inverted.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	257 // RX_UP/DOWN and TX_UP/DOWN
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	258 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	259 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	260 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_7 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	261 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	262
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	263 #define RU_850 ( PA_OFF \| FEM_PINS ^ FEM_9 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	264 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	265 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_7 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	266 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	267
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	268 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	269 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	270 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_8 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	271 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	272
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	273 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	274 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	275 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_8 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	276 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	277
600 8f50b202e81f board preprocessor conditionals: prep for more FC hw in the future Mychaela Falconia <falcon@freecalypso.org> parents: 560 diff changeset	278 #elif defined(CONFIG_TARGET_GTAMODEM)
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	279
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	280 // Openmoko's triband configuration is a bastardized version
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	281 // of TI's quadband one from Leonardo/E-Sample
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	282
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	283 #define FEM_7 BIT_2 // act2
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	284 #define FEM_8 BIT_1 // act1
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	285 #define FEM_9 BIT_4 // act4
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	286
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	287 #define PA_HI_BAND BIT_3 // act3
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	288 #define PA_LO_BAND 0
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	289 #define PA_OFF 0
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	290
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	291 #define FEM_PINS (FEM_7 \| FEM_8 \| FEM_9)
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	292
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	293 #define FEM_OFF ( FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	294
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	295 #define FEM_SLEEP ( 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	296
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	297 // This configuration is always inverted.
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	298
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	299 // RX_UP/DOWN and TX_UP/DOWN
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_9 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	305 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_9 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_7 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	315 #define RU_1900 ( PA_OFF \| FEM_PINS ^ FEM_8 )
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_7 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319
560 d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	320 #elif defined(CONFIG_TARGET_FCFAM)
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	321
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	322 /*
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	323 * In our FreeCalypso hw family, we would like to be able to use
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	324 * both triband and quadband RFFEs. Our current FCDEV3B is triband,
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	325 * copied from Openmoko, and the same is expected to be the case for
600 8f50b202e81f board preprocessor conditionals: prep for more FC hw in the future Mychaela Falconia <falcon@freecalypso.org> parents: 560 diff changeset	326 * future low-budget designs, but if someone pays for a new RF layout,
560 d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	327 * we can use a quadband RFFE instead. If we ever have two different
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	328 * hw platforms or variants that differ in the RFFE but are otherwise
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	329 * firmware-compatible, we would like to have the same fw build
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	330 * work with both triband and quadband RFFEs. How is it possible?
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	331 * The trick is that we define our set of TSPACT RFFE control signals
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	332 * starting with our current OM-based triband version, and add one
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	333 * more signal to support potential future quadband designs.
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	334 */
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	335
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	336 #define FEM_RX_1900 BIT_1 // act1
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	337 #define FEM_TX_HIGH BIT_2 // act2
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	338 #define FEM_TX_LOW BIT_4 // act4
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	339 #define FEM_RX_850 BIT_5 // act5
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	340
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	341 #define PA_HI_BAND BIT_3 // act3
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	342 #define PA_LO_BAND 0
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	343 #define PA_OFF 0
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	344
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	345 #define FEM_PINS (FEM_TX_LOW \| FEM_TX_HIGH \| FEM_RX_850 \| FEM_RX_1900)
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	346
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	347 #define FEM_OFF ( FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	348
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	349 #define FEM_SLEEP ( 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	350
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	351 // This configuration is always inverted.
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	352
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	353 // RX_UP/DOWN and TX_UP/DOWN
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	354 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	355 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	356 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	357 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	358
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	359 #define RU_850 ( PA_OFF \| FEM_PINS ^ FEM_RX_850 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	360 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	361 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	362 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	363
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	364 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	365 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	366 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	367 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	368
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	369 #define RU_1900 ( PA_OFF \| FEM_PINS ^ FEM_RX_1900 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	370 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	371 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	372 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support Mychaela Falconia <falcon@freecalypso.org> parents: 79 diff changeset	373
639 026c98f757a6 tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only Mychaela Falconia <falcon@freecalypso.org> parents: 632 diff changeset	374 #elif defined(CONFIG_TARGET_MGC2GSMT)
608 c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	375
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	376 /*
639 026c98f757a6 tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only Mychaela Falconia <falcon@freecalypso.org> parents: 632 diff changeset	377 * The common MGC2GSMT version of Huawei GTM900-B is very closely based
026c98f757a6 tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only Mychaela Falconia <falcon@freecalypso.org> parents: 632 diff changeset	378 * on Leonardo (2-band version), but the two FEM Tx control signals
026c98f757a6 tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only Mychaela Falconia <falcon@freecalypso.org> parents: 632 diff changeset	379 * are reversed.
608 c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	380 */
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	381
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	382 #define FEM_TX_LOW BIT_1 // act1
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	383 #define FEM_TX_HIGH BIT_2 // act2
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	384
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	385 #define PA_HI_BAND BIT_3 // act3
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	386 #define PA_LO_BAND 0
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	387 #define PA_OFF 0
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	388
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	389 #define FEM_PINS (FEM_TX_LOW \| FEM_TX_HIGH)
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	390
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	391 #define FEM_OFF ( FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	392
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	393 #define FEM_SLEEP ( 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	394
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	395 // This configuration is always inverted.
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	396
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	397 // RX_UP/DOWN and TX_UP/DOWN
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	398 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	399 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	400 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	401 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	402
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	403 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	404 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	405 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	406 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	407
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	408 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	409 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	410 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	411 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	412
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	413 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	414 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	415 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	416 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi Mychaela Falconia <falcon@freecalypso.org> parents: 602 diff changeset	417
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	418 #elif defined(CONFIG_TARGET_PIRELLI)
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	419
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	420 #define ANTSW_RX_PCS BIT_4
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	421 #define ANTSW_TX_HIGH BIT_10
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	422 #define ANTSW_TX_LOW BIT_11
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	424 #define PA_HI_BAND BIT_3 // act3
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	425 #define PA_LO_BAND 0
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	426 #define PA_OFF 0
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	427
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	428 #define PA_ENABLE BIT_0
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	429
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	430 // Pirelli uses a non-inverting buffer
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	431
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	432 #define FEM_OFF ( 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	433
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	434 #define FEM_SLEEP ( 0 )
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	436 // RX_UP/DOWN and TX_UP/DOWN (triband)
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	437 #define RU_900 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	438 #define RD_900 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	439 #define TU_900 ( PA_LO_BAND \| ANTSW_TX_LOW )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	440 #define TD_900 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	441
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	442 #define RU_850 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	443 #define RD_850 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	444 #define TU_850 ( PA_LO_BAND \| ANTSW_TX_LOW )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	445 #define TD_850 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	446
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	447 #define RU_1800 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	448 #define RD_1800 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	449 #define TU_1800 ( PA_HI_BAND \| ANTSW_TX_HIGH )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	450 #define TD_1800 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	451
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	452 #define RU_1900 ( PA_OFF \| ANTSW_RX_PCS )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	453 #define RD_1900 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	454 #define TU_1900 ( PA_HI_BAND \| ANTSW_TX_HIGH )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	455 #define TD_1900 ( PA_OFF \| 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	456
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	457 #elif defined(CONFIG_TARGET_COMPAL)
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	459 #define PA_HI_BAND BIT_8 // act8
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	460 #define PA_LO_BAND 0
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	461 #define PA_OFF 0
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	462
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	463 #define PA_ENABLE BIT_1
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	464
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	465 // FEM control signals are active low
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	466 #define FEM_PINS (BIT_6 \| BIT_2)
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	467
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	468 #define FEM_OFF ( FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	469
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	470 #define FEM_SLEEP ( 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	471
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	472 #define FEM_TX_HIGH BIT_6
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	473 #if USE_TSPACT2_FOR_TXLOW
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	474 #define FEM_TX_LOW BIT_2
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	475 #else
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	476 #define FEM_TX_LOW BIT_6
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	477 #endif
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	479 // RX_UP/DOWN and TX_UP/DOWN
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	480 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	481 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	482 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	483 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	484
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	485 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	486 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	487 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	488 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	490 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	491 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	492 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	493 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	495 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	496 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	497 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	498 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	499
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	500 #endif // FreeCalypso target selection
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 #define TC1_DEVICE_ABB TC1_DEVICE0 // TSPEN0
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	503 #ifdef CONFIG_TARGET_PIRELLI
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	504 #define TC1_DEVICE_RF TC1_DEVICE1 // TSPEN1
3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	505 #else
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506 #define TC1_DEVICE_RF TC1_DEVICE2 // TSPEN2
79 3928363c521f tpudrv12.h: support for multiple targets Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	507 #endif
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510 //--- TIMINGS ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 /------------------------------------------/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513 /* Download delay values */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 /------------------------------------------/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515 // 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 #define T TPU_CLOCK_RANGE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 // - TPU instruction into TSP timings ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521 // 1 tpu instruction = 1 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 #define DLT_1 1 // 1 tpu instruction = 1 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523 #define DLT_2 2 // 2 tpu instruction = 2 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524 #define DLT_3 3 // 3 tpu instruction = 3 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	525 #define DLT_4 4 // 4 tpu instruction = 4 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526 #define SL_SU_DELAY2 DLT_3 // Needed to compile with old l1_rf12
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	528 // - Serialization timings ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529 // The following values where calculated with Katrin Matthes...
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530 //#define SL_7 3 // To send 7 bits to the ABB, 14*T (1/6.5MHz) are needed,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	531 // // i.e. 14 / 6 qbit = 2.333 ~ 3 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532 //#define SL_2B 6 // To send 2 bytes to the RF, 34*T (1/6.5MHz) are needed,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533 // // i.e. 34 / 6 qbit = 5.7 ~ 6 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534 // ... while the following values are based on the HYP004.doc document
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 #define SL_7 2 // To send 7 bits to the ABB, 12*T (1/6.5MHz) are needed,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536 // i.e. 12 / 6 qbit = 2 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537 #define SL_2B 4 // To send 2 bytes to the RF, 21*T (1/6.5MHz) are needed,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 // i.e. 21 / 6 qbit = 3.5 ~ 4 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	539
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540 // - TPU command execution + serialization length ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 #define DLT_1B 4 // 3*move + serialization of 7 bits
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	542 #define DLT_2B 7 // 4*move + serialization of 2 bytes
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543 //#define DLT_1B DLT_3 + SL_7 // 3*move + serialization of 7 bits
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544 //#define DLT_2B DLT_4 + SL_2B // 4*move + serialization of 2 bytes
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547 // - INIT (delta or DLT) timings ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 #define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549 #define DLT_I2 8 // Time required to set RF_SER_OFF
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 #define DLT_I3 5 // Time required to set RF_SER_ON
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551 #define DLT_I4 110 // Regulator Turn-ON time
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554 // - tdt & rdt ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555 // MAX GSM (not GPRS) rdt and tdt values are...
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 //#define rdt 380 // MAX GSM rx delta timing
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	557 //#define tdt 400 // MAX GSM tx delta timing
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	558 // but current rdt and tdt values are...
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 #define rdt 0 // rx delta timing
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560 #define tdt 0 // tx delta timing
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	562 // - RX timings ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563 // - RX down:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	564 // The times below are offsets to when BDLENA goes down
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565 #define TRF_R10 ( 0 - DLT_1B ) // disable BDLENA & BDLON -> power DOWN ABB (end of RX burst), needs DLT_1B to execute
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566 #define TRF_R9 ( - 30 - DLT_2B ) // disable RF SWITCH, power DOWN Rita (go to Idle2 mode)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	567
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568 // - RX up:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	569 // The times below are offsets to when BDLENA goes high
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	570 // Burst data comes here
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	571 #define TRF_R8 ( PROVISION_TIME - 0 - DLT_1B ) // enable BDLENA, disable BDLCAL (I/Q comes 32qbit later)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	572 #define TRF_R7 ( PROVISION_TIME - 7 - DLT_1 ) // enable RF SWITCH
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	573 #define TRF_R6 ( PROVISION_TIME - 67 - DLT_1B ) // enable BDLCAL -> ABB DL filter init
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	574 #define TRF_R5 ( PROVISION_TIME - 72 - DLT_1B ) // enable BDLON -> power ON ABB DL path
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	575 #define TRF_R4 ( PROVISION_TIME - 76 - DLT_2B - rdt ) // power ON RX
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	576 #define TRF_R3 (PROVISION_TIME - 143 - DLT_2B - rdt ) // select the AGC & LNA gains + start DC offset calibration (stops automatically)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	577 //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	578 #define TRF_R2 (PROVISION_TIME - 198 - DLT_2B - rdt ) // set BAND + power ON RX Synth
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	579 #define TRF_R1 (PROVISION_TIME - 208 - DLT_2B - rdt ) // set RX Synth channel
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	580
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	581 // - TX timings ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	582 // - TX down:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	583 // The times below are offsets to when BULENA goes down
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	584
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	585 #if (PA_CTRL_INT == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	586 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	587 #define TRF_T12_5 ( 32 - DLT_2B ) // Power OFF TX loop => power down RF.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	588 #define TRF_T12_3 ( 23 - DLT_1 ) // Disable TXEN.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	589 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	590
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	591 #if (PA_CTRL_INT == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	592 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	593 #define TRF_T12_2 ( 32 - DLT_2B ) // power down RF step 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	594 #define TRF_T12 ( 18 - DLT_2B ) // power down RF step 1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	595 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	596
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	597 #define TRF_T11 ( 0 - DLT_1B ) // disable BULENA -> end of TX burst
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	598 #define TRF_T10_5 ( - 40 - DLT_1B ) // ADC read
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	599
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	600 // - TX up:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	601 // The times below are offsets to when BULENA goes high
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	602 //burst data comes here
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	603 #define TRF_T10_4 ( 22 - DLT_1 ) // enable RF SWITCH + TXEN
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	604 #define TRF_T10 ( 17 - DLT_1 ) // enable RF SWITCH
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	605
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	606 #if (PA_CTRL_INT == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	607 #define TRF_T9 ( 8 - DLT_2B ) // enable PACTRL
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	608 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	609
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	610 #define TRF_T8 ( - 0 - DLT_1B ) // enable BULENA -> start of TX burst
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	611 #define TRF_T7 ( - 50 - DLT_1B - tdt ) // disable BULCAL -> stop ABB UL calibration
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	612 #define TRF_T6 ( - 130 - DLT_1B - tdt ) // enable BULCAL -> start ABB UL calibration
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	613 #define TRF_T5 ( - 158 - DLT_2B - tdt ) // power ON TX
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	614 #define TRF_T4 ( - 190 - DLT_1B - tdt ) // enable BULON -> power ON ABB UL path
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	615 // TRF_T3_MAN_1, TRF_T3_MAN_2 & TRF_T3_MAN_3 are only executed in DCS for PG 2.0 and above
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	616 #define TRF_T3_MAN_3 ( - 239 - DLT_2B - tdt ) // PG2.1: Set the right TX loop charge pump current for DCS & PCS
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	617 #define TRF_T3_MAN_2 ( - 249 - DLT_2B - tdt ) // PG2.1: Go into "TX Manual mode"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	618 #define TRF_T3_MAN_1 ( - 259 - DLT_2B - tdt ) // PG2.1: IN DCS, use manual mode: Copy Serial Interface Registers for "Manual operation"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	619 #define TRF_T3 ( - 259 - DLT_2B - tdt ) // PG2.1: In GSM & PCS go to "Automatic TX mode"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	620 #define TRF_T2 ( - 269 - DLT_2B - tdt ) // PG2.0: set BAND + Power ON Main TX PLL + PACTRL ON
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	621 #define TRF_T1 ( - 279 - DLT_2B - tdt ) // set TX Main PLL channel
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	622

FreeCalypso > hg > fc-magnetite

annotate src/cs/layer1/tpu_drivers/source0/tpudrv12.h @ 639:026c98f757a6