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annotate blobs/patches/main-fchw.patch @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents acb07ce22054
children
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acb07ce22054 blobs/patches: a couple of patched libs imported from tcs211-patches
Mychaela Falconia <falcon@freecalypso.org>
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1 # This patch applies to the Init_Target() function in the init.obj module in
acb07ce22054 blobs/patches: a couple of patched libs imported from tcs211-patches
Mychaela Falconia <falcon@freecalypso.org>
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2 # main.lib; it is an example of how this code will need to be patched for
acb07ce22054 blobs/patches: a couple of patched libs imported from tcs211-patches
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3 # running on our own future FreeCalypso hardware if we choose to use the same
acb07ce22054 blobs/patches: a couple of patched libs imported from tcs211-patches
Mychaela Falconia <falcon@freecalypso.org>
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4 # Spansion S71PL129NC0 flash+pSRAM MCP as used in the Pirelli DP-L10 and use
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5 # the same memory timings as set by Pirelli's firmware.
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7 [init.obj]
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acb07ce22054 blobs/patches: a couple of patched libs imported from tcs211-patches
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9 # value goes into nCS0, nCS1 and nCS3 config registers
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10 .text 66 A4
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11 # value goes into nCS2 config reg
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12 .text 6C A4
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14 # nop out the write into 0x02700000
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16 .text 128 C0
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17 .text 129 46