annotate src/cs/layer1/tpu_drivers/source0/tpudrv12.h @ 646:8c74c177e914

LICENSE: new terms
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 14 Apr 2020 20:09:37 +0000
parents 026c98f757a6
children 3fb7384e820d
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1 /****************** Revision Controle System Header ***********************
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2 * GSM Layer 1 software
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3 * Copyright (c) Texas Instruments 1998
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4 *
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5 * Filename tpudrv12.h
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6 * Copyright 2003 (C) Texas Instruments
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7 *
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8 ****************** Revision Controle System Header ***********************/
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9
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10 //--- Configuration values
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11 #define FEM_TEST 0 // 1 => ENABLE the FEM_TEST mode
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12 #define RF_VERSION 1 // 1 or V1, 5 for V5, etc
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13 #define SAFE_INIT_WA 0 // 1 => ENABLE the "RITA safe init"
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14 // TeST - Enable Main VCO buffer for test
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15 #define MAIN_VCO_ACCESS_WA 0 // 1 => ENABLE the Main VCO buffer
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16
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17 #include "rf.cfg"
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18 #include "fc-target.h"
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19
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20 //--- RITA PG declaration
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21
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22 #define R_PG_10 0
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23 #define R_PG_13 1
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24 #define R_PG_20 2 // For RFPG 2.2, use 2.0
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25 #define R_PG_23 3
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26
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27 //--- PA declaration
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28 #define PA_MGF9009 0
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29 #define PA_RF3146 1
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30 #define PA_RF3133 2
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31 #define PA_PF08123B 3
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32 #define PA_AWT6108 4
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33
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34 #if (RF_PA == PA_MGF9009 || RF_PA == PA_PF08123B)
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35 #define PA_CTRL_INT 0
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36 #else
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37 #define PA_CTRL_INT 1
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38 #endif
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39
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40 //- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0
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41 // AlphaRF7 => "PG #1.3" for TPU purposes (not an official PC number)
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42 // This is also used in l1_rf12.h to select the SWAP_IQ
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43 #if (RF_PG >= R_PG_20)
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44 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
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45 #define PLL2_WA 0 // 0 => DISABLE the PLL2_WA (Rene's "Work-Around")
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46 #define ALPHA_RF7_WA 0 // 0 => DISABLE the Alpha RF7 work-arounds
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47 #elif (RF_PG == R_PG_13)
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48 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
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49 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
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50 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
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51 #else
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52 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
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53 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
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54 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
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55 #endif
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56
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57 //- Bit definitions for TST register programings, etc
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58 #define BIT_0 0x000001
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59 #define BIT_1 0x000002
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60 #define BIT_2 0x000004
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61 #define BIT_3 0x000008
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62 #define BIT_4 0x000010
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63 #define BIT_5 0x000020
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64 #define BIT_6 0x000040
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65 #define BIT_7 0x000080
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66 #define BIT_8 0x000100
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67 #define BIT_9 0x000200
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68 #define BIT_10 0x000400
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69 #define BIT_11 0x000800
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70 #define BIT_12 0x001000
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71 #define BIT_13 0x002000
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72 #define BIT_14 0x004000
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73 #define BIT_15 0x008000
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74 #define BIT_16 0x010000
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75 #define BIT_17 0x020000
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76 #define BIT_18 0x040000
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77 #define BIT_19 0x080000
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78 #define BIT_20 0x100000
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79 #define BIT_21 0x200000
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80 #define BIT_22 0x400000
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81 #define BIT_23 0x800000
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82
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83 //--- TRF6151 definitions ------------------------------------------
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84
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85 //- BASE REGISTER definitions
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86 #define REG_RX 0x000000 // MODE0
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87 #define REG_PLL 0x000001 // MODE1
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88 #define REG_PWR 0x000002 // MODE2
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89 #define REG_CFG 0x000003 // MODE3
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90
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91 //- TeST REGISTER definitions => Used for WA only
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92 // TeST - PLL2 WA => Define PLL2 TEST register
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93 #define TST_PLL2 0x00001E // MODE 14
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94
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95 // TeST - Enable Main VCO buffer for test => Define TST_VCO3 register
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96 #define TST_VCO3 0x00000F // MODE 15 (0*16+15*1)
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97 #define TST_VCO4 0x000024 // MODE 36 (2*16+4*1)
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98
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99 // Alpha RF7 WA TeST registers
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100 #define TST_LDO 0x000027 // MODE 39 (2*16+7*1)
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101 #define TST_PLL1 0x00001D // MODE 29 (1*16+13*1)
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102 #define TST_TX2 0x000037 // MODE 55 (3*16+7*1)
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103
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104 // More Alpha RF7 WA TeST registers
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105 #define TST_TX3 0x00003C // MODE 61 (3*16+12*1)
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106 #define TST_TX4 0x00003D // MODE 61 (3*16+13*1)
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107
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108 // PG 2.1 WA TeST registers
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109 #define TST_PLL3 0x00001F // MODE 31 (1*16+15*1)
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110 // #define TST_PLL4 0x00002C // MODE 44 (2*16+12*1)
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111 #define TST_MISC 0x00003E // MODE 62 (3*16+14*1) => Used for setting the VCXO current
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112 #define TST_LO 0x00001C // MODE 28 (1*16+12*1)
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113
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114 // Registers used to improve the Modulation Spectrum in DCS/PCS for PG2.1 V1
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115 // UPDATE_SERIAL_REGISTER_COPY is a "dummy addres" that,
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116 // when accessed, triggers the copy of the serial registers.
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117 // This is necessary to switch into "manual operation mode"
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118 #define UPDATE_SERIAL_INTERFACE_COPY 0x000007
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119 #define TX_LOOP_MANUAL BIT_3
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120
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121
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122 //- REG_RX - MODE0
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123 #define BLOCK_DETECT_0 BIT_3
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124 #define BLOCK_DETECT_1 BIT_4
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125 #define RST_BLOCK_DETECT_0 BIT_5
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126 #define RST_BLOCK_DETECT_1 BIT_6
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127 #define READ_EN BIT_7
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128 #define RX_CAL_MODE BIT_8
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129 #define RF_GAIN (BIT_10 | BIT_9)
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130
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131
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132 //- REG_PLL - MODE1
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133 //PLL_REGB
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134 //PLL_REGA
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135
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136 //- REG_PWR - MODE2
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137 #define BANDGAP_MODE_OFF 0x0
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138 #define BANDGAP_MODE_ON_ENA BIT_4
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139 #define BANDGAP_MODE_ON_DIS (BIT_4 | BIT_3)
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140 #define REGUL_MODE_ON BIT_5
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141 // BIT[8..6] band
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142 #define BAND_SELECT_GSM BIT_6
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143 #define BAND_SELECT_DCS BIT_7
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144 #define BAND_SELECT_850_LO BIT_8
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145 #define BAND_SELECT_850_HI (BIT_8 | BIT_6)
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146 #define BAND_SELECT_PCS (BIT_8 | BIT_7)
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147
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148 #define SYNTHE_MODE_OFF 0x0
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149 #define SYNTHE_MODE_RX BIT_9
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150 #define SYNTHE_MODE_TX BIT_10
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151 #define RX_MODE_OFF 0x0
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152 #define RX_MODE_A BIT_11
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153 #define RX_MODE_B1 BIT_12
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154 #define RX_MODE_B2 (BIT_12 | BIT_11)
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155 #define TX_MODE_OFF 0x0
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156 #define TX_MODE_ON BIT_13
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157 #define PACTRL_APC_OFF 0x0
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158 #define PACTRL_APC_ON BIT_14
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159 #define PACTRL_APC_DIS 0x0
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160 #define PACTRL_APC_ENA BIT_15
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161
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162
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163 //- REG_CFG - MODE3
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164 // Common PA controller settings:
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165 #define PACTRL_TYPE_PWR 0x0
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166 #define PACTRL_TYPE_CUR BIT_3
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167 #define PACTRL_IDIOD_30_UA 0x0
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168 #define PACTRL_IDIOD_300_UA BIT_4
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169
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170 // PA controller Clara-like (Power Sensing) settings:
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171 #define PACTRL_VHOME_610_MV (BIT_7 | BIT_5)
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172 #define PACTRL_VHOME_839_MV (BIT_7 | BIT_5)
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173 #define PACTRL_VHOME_1000_MV (BIT_6 | BIT_9)
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174 #define PACTRL_VHOME_1600_MV (BIT_8 | BIT_5)
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175 #define PACTRL_RES_OPEN 0x0
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176 #define PACTRL_RES_150_K BIT_10
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177 #define PACTRL_RES_300_K BIT_11
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178 #define PACTRL_RES_NU (BIT_10 | BIT_11)
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179 #define PACTRL_CAP_0_PF 0x0
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180 #define PACTRL_CAP_12_5_PF BIT_12
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181 #define PACTRL_CAP_25_PF (BIT_13 | BIT_12)
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182 #define PACTRL_CAP_50_PF BIT_13
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183
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184 // PACTRL_CFG contains the configuration of the PACTRL that will
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185 // be put into the REG_CFG register at initialization time
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186 // WARNING - Do not forget to set the PACTRL_TYPE (PWR or CUR)
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187 // in this #define!!!
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188 #if (RF_PA == 0) // MGF9009 (LCPA)
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189 #define PACTRL_CFG \
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190 PACTRL_IDIOD_300_UA | \
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191 PACTRL_CAP_25_PF | \
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192 PACTRL_VHOME_1000_MV | \
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193 PACTRL_RES_300_K
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194 #elif (RF_PA == 1) // 3146
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195 #define PACTRL_CFG 0
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196
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197 #elif (RF_PA == 2) // 3133
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198 #define PACTRL_CFG 0
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199
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200 #elif (RF_PA == 3) // PF08123B
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201 #define PACTRL_CFG \
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202 PACTRL_TYPE_PWR | \
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203 PACTRL_CAP_50_PF | \
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204 PACTRL_RES_300_K | \
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205 PACTRL_VHOME_610_MV
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206 #elif (RF_PA == 4) // AWT6108
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207 #define PACTRL_CFG 0
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208 #else
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209 #error Unknown PA specifiec!
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210 #endif
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211
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212 // Temperature sensor
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213 #define TEMP_SENSOR_OFF 0x0
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214 #define TEMP_SENSOR_ON BIT_14
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215 // Internal Logic Init Disable
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216 #define ILOGIC_INIT_DIS BIT_15
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217 // ILOGIC_INIT_DIS must be ALWAYS set when programming the REG_CFG register
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218 // It was introduced in PG 1.2
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219 // For previous PGs this BIT was unused, so it can be safelly programmed
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220 // for all PGs
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221
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222
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223 // RF signals connected to TSPACT [0..7]
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224
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225 #ifdef CONFIG_TARGET_PIRELLI
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226 #define RF_RESET_LINE BIT_5
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227 #else
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228 #define RF_RESET_LINE BIT_0
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229 #endif
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230
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231 #define RF_SER_ON RF_RESET_LINE
0
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232 #define RF_SER_OFF 0
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233
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234 #define TEST_TX_ON 0
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235 #define TEST_RX_ON 0
0
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236
632
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237 #if defined(CONFIG_TARGET_LEONARDO) || defined(CONFIG_TARGET_ESAMPLE) || \
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238 defined(CONFIG_TARGET_TANGO)
0
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239
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240 // 4-band config (E-sample, P2, Leonardo)
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241 #define FEM_7 BIT_2 // act2
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242 #define FEM_8 BIT_1 // act1
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243 #define FEM_9 BIT_4 // act4
0
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244
79
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245 #define PA_HI_BAND BIT_3 // act3
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246 #define PA_LO_BAND 0
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247 #define PA_OFF 0
0
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248
79
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249 #define FEM_PINS (FEM_7 | FEM_8 | FEM_9)
0
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250
79
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251 #define FEM_OFF ( FEM_PINS ^ 0 )
0
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252
79
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253 #define FEM_SLEEP ( 0 )
0
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254
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255 // This configuration is always inverted.
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256
79
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257 // RX_UP/DOWN and TX_UP/DOWN
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258 #define RU_900 ( PA_OFF | FEM_PINS ^ 0 )
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259 #define RD_900 ( PA_OFF | FEM_PINS ^ 0 )
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260 #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_7 )
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261 #define TD_900 ( PA_OFF | FEM_PINS ^ 0 )
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262
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263 #define RU_850 ( PA_OFF | FEM_PINS ^ FEM_9 )
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264 #define RD_850 ( PA_OFF | FEM_PINS ^ 0 )
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265 #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_7 )
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266 #define TD_850 ( PA_OFF | FEM_PINS ^ 0 )
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267
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268 #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 )
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269 #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 )
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270 #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_8 )
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271 #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 )
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272
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273 #define RU_1900 ( PA_OFF | FEM_PINS ^ 0 )
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274 #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 )
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275 #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_8 )
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276 #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 )
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277
600
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278 #elif defined(CONFIG_TARGET_GTAMODEM)
79
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279
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280 // Openmoko's triband configuration is a bastardized version
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281 // of TI's quadband one from Leonardo/E-Sample
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282
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283 #define FEM_7 BIT_2 // act2
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284 #define FEM_8 BIT_1 // act1
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285 #define FEM_9 BIT_4 // act4
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286
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287 #define PA_HI_BAND BIT_3 // act3
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288 #define PA_LO_BAND 0
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289 #define PA_OFF 0
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290
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291 #define FEM_PINS (FEM_7 | FEM_8 | FEM_9)
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292
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293 #define FEM_OFF ( FEM_PINS ^ 0 )
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294
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295 #define FEM_SLEEP ( 0 )
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296
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297 // This configuration is always inverted.
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298
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299 // RX_UP/DOWN and TX_UP/DOWN
0
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300 #define RU_900 ( PA_OFF | FEM_PINS ^ 0 )
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301 #define RD_900 ( PA_OFF | FEM_PINS ^ 0 )
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302 #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_9 )
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303 #define TD_900 ( PA_OFF | FEM_PINS ^ 0 )
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304
79
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305 #define RU_850 ( PA_OFF | FEM_PINS ^ 0 )
0
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306 #define RD_850 ( PA_OFF | FEM_PINS ^ 0 )
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307 #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_9 )
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308 #define TD_850 ( PA_OFF | FEM_PINS ^ 0 )
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309
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310 #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 )
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311 #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 )
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312 #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_7 )
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313 #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 )
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314
79
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315 #define RU_1900 ( PA_OFF | FEM_PINS ^ FEM_8 )
0
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316 #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 )
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317 #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_7 )
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318 #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 )
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319
560
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320 #elif defined(CONFIG_TARGET_FCFAM)
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321
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322 /*
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323 * In our FreeCalypso hw family, we would like to be able to use
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324 * both triband and quadband RFFEs. Our current FCDEV3B is triband,
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325 * copied from Openmoko, and the same is expected to be the case for
600
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326 * future low-budget designs, but if someone pays for a new RF layout,
560
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327 * we can use a quadband RFFE instead. If we ever have two different
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328 * hw platforms or variants that differ in the RFFE but are otherwise
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329 * firmware-compatible, we would like to have the same fw build
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330 * work with both triband and quadband RFFEs. How is it possible?
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331 * The trick is that we define our set of TSPACT RFFE control signals
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332 * starting with our current OM-based triband version, and add one
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333 * more signal to support potential future quadband designs.
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334 */
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335
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336 #define FEM_RX_1900 BIT_1 // act1
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337 #define FEM_TX_HIGH BIT_2 // act2
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338 #define FEM_TX_LOW BIT_4 // act4
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339 #define FEM_RX_850 BIT_5 // act5
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340
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341 #define PA_HI_BAND BIT_3 // act3
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342 #define PA_LO_BAND 0
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343 #define PA_OFF 0
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344
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345 #define FEM_PINS (FEM_TX_LOW | FEM_TX_HIGH | FEM_RX_850 | FEM_RX_1900)
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346
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347 #define FEM_OFF ( FEM_PINS ^ 0 )
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348
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349 #define FEM_SLEEP ( 0 )
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350
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351 // This configuration is always inverted.
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352
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353 // RX_UP/DOWN and TX_UP/DOWN
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354 #define RU_900 ( PA_OFF | FEM_PINS ^ 0 )
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355 #define RD_900 ( PA_OFF | FEM_PINS ^ 0 )
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356 #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_TX_LOW )
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357 #define TD_900 ( PA_OFF | FEM_PINS ^ 0 )
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diff changeset
358
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
359 #define RU_850 ( PA_OFF | FEM_PINS ^ FEM_RX_850 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
360 #define RD_850 ( PA_OFF | FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
361 #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_TX_LOW )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
362 #define TD_850 ( PA_OFF | FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
363
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
364 #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
365 #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
366 #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_TX_HIGH )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
367 #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
368
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
369 #define RU_1900 ( PA_OFF | FEM_PINS ^ FEM_RX_1900 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
370 #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
371 #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_TX_HIGH )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
372 #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 )
d380b62e1019 tpudrv12.h: provision for future FCFAM triband-or-quadband support
Mychaela Falconia <falcon@freecalypso.org>
parents: 79
diff changeset
373
639
026c98f757a6 tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only
Mychaela Falconia <falcon@freecalypso.org>
parents: 632
diff changeset
374 #elif defined(CONFIG_TARGET_MGC2GSMT)
608
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
375
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
376 /*
639
026c98f757a6 tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only
Mychaela Falconia <falcon@freecalypso.org>
parents: 632
diff changeset
377 * The common MGC2GSMT version of Huawei GTM900-B is very closely based
026c98f757a6 tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only
Mychaela Falconia <falcon@freecalypso.org>
parents: 632
diff changeset
378 * on Leonardo (2-band version), but the two FEM Tx control signals
026c98f757a6 tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only
Mychaela Falconia <falcon@freecalypso.org>
parents: 632
diff changeset
379 * are reversed.
608
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
380 */
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
381
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
382 #define FEM_TX_LOW BIT_1 // act1
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
383 #define FEM_TX_HIGH BIT_2 // act2
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
384
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
385 #define PA_HI_BAND BIT_3 // act3
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
386 #define PA_LO_BAND 0
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
387 #define PA_OFF 0
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
388
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
389 #define FEM_PINS (FEM_TX_LOW | FEM_TX_HIGH)
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
390
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
391 #define FEM_OFF ( FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
392
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
393 #define FEM_SLEEP ( 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
394
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
395 // This configuration is always inverted.
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
396
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
397 // RX_UP/DOWN and TX_UP/DOWN
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
398 #define RU_900 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
399 #define RD_900 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
400 #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_TX_LOW )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
401 #define TD_900 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
402
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
403 #define RU_850 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
404 #define RD_850 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
405 #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_TX_LOW )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
406 #define TD_850 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
407
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
408 #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
409 #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
410 #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_TX_HIGH )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
411 #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
412
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
413 #define RU_1900 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
414 #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
415 #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_TX_HIGH )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
416 #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 )
c09a1ca60d57 proper GTM900 target with TPU config per Songbosi
Mychaela Falconia <falcon@freecalypso.org>
parents: 602
diff changeset
417
79
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
418 #elif defined(CONFIG_TARGET_PIRELLI)
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
419
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
420 #define ANTSW_RX_PCS BIT_4
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
421 #define ANTSW_TX_HIGH BIT_10
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
422 #define ANTSW_TX_LOW BIT_11
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423
79
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
424 #define PA_HI_BAND BIT_3 // act3
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
425 #define PA_LO_BAND 0
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
426 #define PA_OFF 0
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
427
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
428 #define PA_ENABLE BIT_0
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
429
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
430 // Pirelli uses a non-inverting buffer
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
431
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
432 #define FEM_OFF ( 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
433
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
434 #define FEM_SLEEP ( 0 )
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435
79
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
436 // RX_UP/DOWN and TX_UP/DOWN (triband)
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
437 #define RU_900 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
438 #define RD_900 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
439 #define TU_900 ( PA_LO_BAND | ANTSW_TX_LOW )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
440 #define TD_900 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
441
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
442 #define RU_850 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
443 #define RD_850 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
444 #define TU_850 ( PA_LO_BAND | ANTSW_TX_LOW )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
445 #define TD_850 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
446
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
447 #define RU_1800 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
448 #define RD_1800 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
449 #define TU_1800 ( PA_HI_BAND | ANTSW_TX_HIGH )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
450 #define TD_1800 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
451
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
452 #define RU_1900 ( PA_OFF | ANTSW_RX_PCS )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
453 #define RD_1900 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
454 #define TU_1900 ( PA_HI_BAND | ANTSW_TX_HIGH )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
455 #define TD_1900 ( PA_OFF | 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
456
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
457 #elif defined(CONFIG_TARGET_COMPAL)
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458
79
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
459 #define PA_HI_BAND BIT_8 // act8
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
460 #define PA_LO_BAND 0
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
461 #define PA_OFF 0
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
462
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
463 #define PA_ENABLE BIT_1
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
464
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
465 // FEM control signals are active low
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
466 #define FEM_PINS (BIT_6 | BIT_2)
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
467
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
468 #define FEM_OFF ( FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
469
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
470 #define FEM_SLEEP ( 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
471
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
472 #define FEM_TX_HIGH BIT_6
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
473 #if USE_TSPACT2_FOR_TXLOW
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
474 #define FEM_TX_LOW BIT_2
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
475 #else
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
476 #define FEM_TX_LOW BIT_6
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
477 #endif
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478
79
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
479 // RX_UP/DOWN and TX_UP/DOWN
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
480 #define RU_900 ( PA_OFF | FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
481 #define RD_900 ( PA_OFF | FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
482 #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_TX_LOW )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
483 #define TD_900 ( PA_OFF | FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
484
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
485 #define RU_850 ( PA_OFF | FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
486 #define RD_850 ( PA_OFF | FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
487 #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_TX_LOW )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
488 #define TD_850 ( PA_OFF | FEM_PINS ^ 0 )
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489
79
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
490 #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
491 #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
492 #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_TX_HIGH )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
493 #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 )
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494
79
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
495 #define RU_1900 ( PA_OFF | FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
496 #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
497 #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_TX_HIGH )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
498 #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 )
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
499
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
500 #endif // FreeCalypso target selection
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502 #define TC1_DEVICE_ABB TC1_DEVICE0 // TSPEN0
79
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
503 #ifdef CONFIG_TARGET_PIRELLI
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
504 #define TC1_DEVICE_RF TC1_DEVICE1 // TSPEN1
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
505 #else
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506 #define TC1_DEVICE_RF TC1_DEVICE2 // TSPEN2
79
3928363c521f tpudrv12.h: support for multiple targets
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
507 #endif
0
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510 //--- TIMINGS ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
512 /*------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
513 /* Download delay values */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
514 /*------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
515 // 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
516
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
517 #define T TPU_CLOCK_RANGE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
518
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
519
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
520 // - TPU instruction into TSP timings ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
521 // 1 tpu instruction = 1 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
522 #define DLT_1 1 // 1 tpu instruction = 1 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
523 #define DLT_2 2 // 2 tpu instruction = 2 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
524 #define DLT_3 3 // 3 tpu instruction = 3 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
525 #define DLT_4 4 // 4 tpu instruction = 4 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
526 #define SL_SU_DELAY2 DLT_3 // Needed to compile with old l1_rf12
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
527
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
528 // - Serialization timings ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
529 // The following values where calculated with Katrin Matthes...
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
530 //#define SL_7 3 // To send 7 bits to the ABB, 14*T (1/6.5MHz) are needed,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
531 // // i.e. 14 / 6 qbit = 2.333 ~ 3 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
532 //#define SL_2B 6 // To send 2 bytes to the RF, 34*T (1/6.5MHz) are needed,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
533 // // i.e. 34 / 6 qbit = 5.7 ~ 6 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
534 // ... while the following values are based on the HYP004.doc document
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
535 #define SL_7 2 // To send 7 bits to the ABB, 12*T (1/6.5MHz) are needed,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
536 // i.e. 12 / 6 qbit = 2 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
537 #define SL_2B 4 // To send 2 bytes to the RF, 21*T (1/6.5MHz) are needed,
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
538 // i.e. 21 / 6 qbit = 3.5 ~ 4 qbit
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
539
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
540 // - TPU command execution + serialization length ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
541 #define DLT_1B 4 // 3*move + serialization of 7 bits
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
542 #define DLT_2B 7 // 4*move + serialization of 2 bytes
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
543 //#define DLT_1B DLT_3 + SL_7 // 3*move + serialization of 7 bits
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
544 //#define DLT_2B DLT_4 + SL_2B // 4*move + serialization of 2 bytes
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
545
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
546
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
547 // - INIT (delta or DLT) timings ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
548 #define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
549 #define DLT_I2 8 // Time required to set RF_SER_OFF
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
550 #define DLT_I3 5 // Time required to set RF_SER_ON
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
551 #define DLT_I4 110 // Regulator Turn-ON time
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
552
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
553
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
554 // - tdt & rdt ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
555 // MAX GSM (not GPRS) rdt and tdt values are...
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
556 //#define rdt 380 // MAX GSM rx delta timing
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
557 //#define tdt 400 // MAX GSM tx delta timing
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
558 // but current rdt and tdt values are...
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
559 #define rdt 0 // rx delta timing
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
560 #define tdt 0 // tx delta timing
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
561
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
562 // - RX timings ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
563 // - RX down:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
564 // The times below are offsets to when BDLENA goes down
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
565 #define TRF_R10 ( 0 - DLT_1B ) // disable BDLENA & BDLON -> power DOWN ABB (end of RX burst), needs DLT_1B to execute
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
566 #define TRF_R9 ( - 30 - DLT_2B ) // disable RF SWITCH, power DOWN Rita (go to Idle2 mode)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
567
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
568 // - RX up:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
569 // The times below are offsets to when BDLENA goes high
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
570 // Burst data comes here
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
571 #define TRF_R8 ( PROVISION_TIME - 0 - DLT_1B ) // enable BDLENA, disable BDLCAL (I/Q comes 32qbit later)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
572 #define TRF_R7 ( PROVISION_TIME - 7 - DLT_1 ) // enable RF SWITCH
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
573 #define TRF_R6 ( PROVISION_TIME - 67 - DLT_1B ) // enable BDLCAL -> ABB DL filter init
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
574 #define TRF_R5 ( PROVISION_TIME - 72 - DLT_1B ) // enable BDLON -> power ON ABB DL path
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
575 #define TRF_R4 ( PROVISION_TIME - 76 - DLT_2B - rdt ) // power ON RX
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
576 #define TRF_R3 (PROVISION_TIME - 143 - DLT_2B - rdt ) // select the AGC & LNA gains + start DC offset calibration (stops automatically)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
577 //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
578 #define TRF_R2 (PROVISION_TIME - 198 - DLT_2B - rdt ) // set BAND + power ON RX Synth
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
579 #define TRF_R1 (PROVISION_TIME - 208 - DLT_2B - rdt ) // set RX Synth channel
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
580
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
581 // - TX timings ---
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
582 // - TX down:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
583 // The times below are offsets to when BULENA goes down
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
584
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
585 #if (PA_CTRL_INT == 1)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
586 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
587 #define TRF_T12_5 ( 32 - DLT_2B ) // Power OFF TX loop => power down RF.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
588 #define TRF_T12_3 ( 23 - DLT_1 ) // Disable TXEN.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
589 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
590
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
591 #if (PA_CTRL_INT == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
592 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
593 #define TRF_T12_2 ( 32 - DLT_2B ) // power down RF step 2
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
594 #define TRF_T12 ( 18 - DLT_2B ) // power down RF step 1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
595 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
596
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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597 #define TRF_T11 ( 0 - DLT_1B ) // disable BULENA -> end of TX burst
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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598 #define TRF_T10_5 ( - 40 - DLT_1B ) // ADC read
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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599
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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600 // - TX up:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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601 // The times below are offsets to when BULENA goes high
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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602 //burst data comes here
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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603 #define TRF_T10_4 ( 22 - DLT_1 ) // enable RF SWITCH + TXEN
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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604 #define TRF_T10 ( 17 - DLT_1 ) // enable RF SWITCH
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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605
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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606 #if (PA_CTRL_INT == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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607 #define TRF_T9 ( 8 - DLT_2B ) // enable PACTRL
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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608 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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609
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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610 #define TRF_T8 ( - 0 - DLT_1B ) // enable BULENA -> start of TX burst
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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611 #define TRF_T7 ( - 50 - DLT_1B - tdt ) // disable BULCAL -> stop ABB UL calibration
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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612 #define TRF_T6 ( - 130 - DLT_1B - tdt ) // enable BULCAL -> start ABB UL calibration
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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613 #define TRF_T5 ( - 158 - DLT_2B - tdt ) // power ON TX
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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614 #define TRF_T4 ( - 190 - DLT_1B - tdt ) // enable BULON -> power ON ABB UL path
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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615 // TRF_T3_MAN_1, TRF_T3_MAN_2 & TRF_T3_MAN_3 are only executed in DCS for PG 2.0 and above
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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616 #define TRF_T3_MAN_3 ( - 239 - DLT_2B - tdt ) // PG2.1: Set the right TX loop charge pump current for DCS & PCS
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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617 #define TRF_T3_MAN_2 ( - 249 - DLT_2B - tdt ) // PG2.1: Go into "TX Manual mode"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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618 #define TRF_T3_MAN_1 ( - 259 - DLT_2B - tdt ) // PG2.1: IN DCS, use manual mode: Copy Serial Interface Registers for "Manual operation"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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619 #define TRF_T3 ( - 259 - DLT_2B - tdt ) // PG2.1: In GSM & PCS go to "Automatic TX mode"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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620 #define TRF_T2 ( - 269 - DLT_2B - tdt ) // PG2.0: set BAND + Power ON Main TX PLL + PACTRL ON
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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621 #define TRF_T1 ( - 279 - DLT_2B - tdt ) // set TX Main PLL channel
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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622