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annotate src/cs/drivers/drv_core/inth/sys_inth.h @ 0:945cf7f506b2

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src/cs: chipsetsw import from tcs211-fcmodem binary blobs and LCD demo files have been excluded, all line endings are LF only
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 25 Sep 2016 22:50:11 +0000
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1 /* @(#) nom : sys_inth.h SID: 1.2 date : 05/23/03 */
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2 /* Filename: sys_inth.h */
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3 /* Version: 1.2 */
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4 /******************************************************************************
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5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT
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6 *
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7 * (C) 2002 Texas Instruments France. All rights reserved
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8 *
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9 * Author : Francois AMAND
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10 *
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11 *
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12 * Important Note
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13 * --------------
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14 *
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15 * This S/W is a preliminary version. It contains information on a product
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16 * under development and is issued for evaluation purposes only. Features
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17 * characteristics, data and other information are subject to change.
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18 *
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19 * The S/W is furnished under Non Disclosure Agreement and may be used or
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20 * copied only in accordance with the terms of the agreement. It is an offence
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21 * to copy the software in any way except as specifically set out in the
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22 * agreement. No part of this document may be reproduced or transmitted in any
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23 * form or by any means, electronic or mechanical, including photocopying and
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24 * recording, for any purpose without the express written permission of Texas
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25 * Instruments Inc.
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26 *
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27 ******************************************************************************
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28 *
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29 * FILE NAME: sys_inth.h
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30 *
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31 *
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32 * PURPOSE: Header file for the Interrupt Handler Driver.
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33 *
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34 *
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35 * FILE REFERENCES:
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36 *
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37 * Name IO Description
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38 * ------------- -- ---------------------------------------------
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39 *
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40 *
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41 *
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42 * EXTERNAL VARIABLES:
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43 *
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44 * Source:
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45 *
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46 * Name Type IO Description
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47 * ------------- --------------- -- ------------------------------
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48 *
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49 *
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50 *
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51 * EXTERNAL REFERENCES:
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52 *
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53 * Name Description
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54 * ------------------ -------------------------------------------------------
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55 *
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56 *
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57 *
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58 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES:
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59 *
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60 *
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61 *
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62 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS:
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63 *
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64 *
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65 *
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66 * NOTES:
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67 *
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68 *
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69 *
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70 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES:
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71 *
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72 *
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73 *
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74 *
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75 * DEVELOPMENT HISTORY:
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76 *
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77 * Date Name(s) Version Description
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78 * ----------- -------------- ------- -------------------------------------
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79 * 11-Oct-2002 Francois AMAND 0.0.1 First implementation
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80 *
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81 * ALGORITHM:
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82 *
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83 *
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84 *****************************************************************************/
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85
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86 #include "l1sw.cfg"
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87 #include "chipset.cfg"
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88
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89 #if (CHIPSET == 12)
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90
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91 #ifndef __SYS_INTH_H__
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92 #define __SYS_INTH_H__
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93
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94 #if (OP_L1_STANDALONE == 0)
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95 #include "main/sys_types.h"
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96 #else
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97 #include "sys_types.h"
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98 #endif
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99 #include "sys_map.h"
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100
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101
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102 /*
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103 * Driver version
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104 */
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105 #define C_INTH_DRIVER_VERSION 0x0001
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106
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107
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108 /*
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109 * Number of interrupts
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110 */
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111 #define C_INTH_NUM_INT 32
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112 #define C_INTH_2ND_NUM_INT 5
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113
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114 #define C_INTH_NB_INTERRUPT (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)
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115
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116
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117 /*
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118 * Main INTH : Interrupt bit numbers
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119 */
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120 #define C_INTH_WATCHDOG_IT 0
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121 #define C_INTH_TIMER1_IT 1
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122 #define C_INTH_TIMER2_IT 2
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123 #define C_INTH_TSP_RECEIVE_IT 3
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124 #define C_INTH_FRAME_IT 4
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125 #define C_INTH_PAGE_IT 5
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126 #define C_INTH_SIM_IT 6
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127 #define C_INTH_UART_MODEM1_IT 7
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128 #define C_INTH_KEYBOARD_IT 8
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129 #define C_INTH_RTC_TIMER_IT 9
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130 #define C_INTH_RTC_ALARM_IT 10
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131 #define C_INTH_ULPD_GAUGING_IT 11
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132 #define C_INTH_ABB_IRQ_IT 12
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133 #define C_INTH_SPIv 13
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134 #define C_INTH_DMA_IT 14
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135 #define C_INTH_API_IT 15
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136 #define C_INTH_GPIO_IT 16
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137 #define C_INTH_ABB_FIQ_IT 17
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138 #define C_INTH_UART_IRDA_IT 18
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139 #define C_INTH_TGSM_IT 19
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140 #define C_INTH_GEA_IT 20
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141 #define C_INTH_EXT_IRQ1_IT 21
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142 #define C_INTH_EXT_IRQ2_IT 22
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143 #define C_INTH_USIM_CD_IT 23
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144 #define C_INTH_USIM_IT 24
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145 #define C_INTH_LCD_IT 25
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146 #define C_INTH_USB_IT 26
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147 #define C_INTH_MMC_SD_MS_IT 27
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148 #define C_INTH_UART_MODEM2_IT 28
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149 #define C_INTH_2ND_INTH_IT 29
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150 #define C_INTH_I2C_IT 30
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151 #define C_INTH_NAND_FLASH_IT 31
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152
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153 /*
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154 * Second INTH : Interrupt bit numbers
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155 */
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156 #define C_INTH_RNG_IT 32
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157 #define C_INTH_SHA1_MD5_IT 33
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158 #define C_INTH_EMPU_IT 34
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159 #define C_INTH_SEC_DMA_IT 35
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160 #define C_INTH_SEC_TIMER_IT 36
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161
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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162
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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163 /*
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164 * Address of the Main interrupt handler registers
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165 */
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166 #define C_INTH_IT_REG1 C_MAP_INTH_BASE /* INTH IT register 1 */
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167 #define C_INTH_IT_REG2 (C_MAP_INTH_BASE + 0x02) /* INTH IT register 2 */
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168 #define C_INTH_MASK_REG1 (C_MAP_INTH_BASE + 0x08) /* INTH mask register 1 */
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169 #define C_INTH_MASK_REG2 (C_MAP_INTH_BASE + 0x0a) /* INTH mask register 2 */
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170 #define C_INTH_B_IRQ_REG (C_MAP_INTH_BASE + 0x10) /* INTH source binary IRQ reg. */
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171 #define C_INTH_B_FIQ_REG (C_MAP_INTH_BASE + 0x12) /* INTH source binary FIQ reg. */
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172 #define C_INTH_CTRL_REG (C_MAP_INTH_BASE + 0x14) /* INTH control register */
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173 #define C_INTH_EXT_REG (C_MAP_INTH_BASE + 0x20) /* INTH 1st external int. reg. */
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174
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175 /*
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176 * Address of the Second interrupt handler registers
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177 */
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178 #define C_INTH2_IT_REG1 C_MAP_INTH_SEC_BASE /* INTH IT register 1 */
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179 #define C_INTH2_MASK_REG1 (C_MAP_INTH_SEC_BASE + 0x08) /* INTH mask register 1 */
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180 #define C_INTH2_B_IRQ_REG (C_MAP_INTH_SEC_BASE + 0x10) /* INTH source binary IRQ reg. */
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181 #define C_INTH2_CTRL_REG (C_MAP_INTH_SEC_BASE + 0x14) /* INTH control register */
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182 #define C_INTH2_EXT_REG (C_MAP_INTH_SEC_BASE + 0x20) /* INTH 1st external int. reg. */
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183
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184
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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185 /*
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186 * INTH_B_x_REG definition
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187 */
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188 #define C_INTH_SRC_NUM 0x001f
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189 #define C_INTH2_SRC_NUM 0x0007
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190
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191 /*
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192 * ILR_IRQx_REG definition
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193 */
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194 #define C_INTH_IRQ 0
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195 #define C_INTH_FIQ 1
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196
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197 #define C_INTH_LEVEL 0
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198 #define C_INTH_EDGE 1
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199
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200
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201
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202 /****************************************************************************
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203 * MACRO DEFINITION
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204 ***************************************************************************/
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205
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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206 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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207 *
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208 * MACRO NAME: F_INTH_ENABLE_ONE_IT
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209 * Enable the interrupt specified in argument.
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210 *
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211 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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212 * ARGUMENT LIST:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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213 *
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214 * Argument Description
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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215 * ------------ ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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216 * d_it Interrupt index
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217 *
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218 * RETURN VALUE: None
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219 *
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220 ***************************************************************************/
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221
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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222 #define F_INTH_ENABLE_ONE_IT(d_it) { \
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223 if (d_it < 16) \
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224 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG1 &= ~(1 << d_it); \
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225 else if (d_it < C_INTH_NUM_INT) \
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226 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG2 &= ~(1 << (d_it-16)); \
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227 else if (d_it < (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)) \
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228 * (volatile SYS_UWORD16 *) C_INTH2_MASK_REG1 &= ~(1 << (d_it-32)); \
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229 }
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230
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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231
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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232
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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233 /****************************************************************************
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234 *
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235 * MACRO NAME: F_INTH_DISABLE_ONE_IT
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236 * Disable the interrupt specified in argument.
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237 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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238 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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239 * ARGUMENT LIST:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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240 *
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Mychaela Falconia <falcon@freecalypso.org>
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241 * Argument Description
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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242 * ------------ ----------------------------------------------------------
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Mychaela Falconia <falcon@freecalypso.org>
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243 * d_it Interrupt index
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Mychaela Falconia <falcon@freecalypso.org>
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244 *
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Mychaela Falconia <falcon@freecalypso.org>
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245 * RETURN VALUE: None
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Mychaela Falconia <falcon@freecalypso.org>
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246 *
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Mychaela Falconia <falcon@freecalypso.org>
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247 ***************************************************************************/
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Mychaela Falconia <falcon@freecalypso.org>
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248
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 #define F_INTH_DISABLE_ONE_IT(d_it) { \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 if (d_it < 16) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG1 |= (1 << d_it); \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 else if (d_it < C_INTH_NUM_INT) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG2 |= (1 << (d_it-16)); \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 else if (d_it < (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 * (volatile SYS_UWORD16 *) C_INTH2_MASK_REG1 |= (1 << (d_it-32)); \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 * MACRO NAME: F_INTH_DISABLE_ALL_IT
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 * Disable all interrupts.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 * ARGUMENT LIST:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 * Argument Description
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 * ------------ ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 * RETURN VALUE: None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 #define F_INTH_DISABLE_ALL_IT { \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG1 = 0xffff; \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 * (volatile SYS_UWORD16 *) C_INTH_MASK_REG2 = 0xffff; \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 * (volatile SYS_UWORD16 *) C_INTH2_MASK_REG1 = 0x001f; \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 * MACRO NAME: F_INTH_RESET_ALL_IT
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 * Reset all interrupts.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 * ARGUMENT LIST:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 * Argument Description
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 * ------------ ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 * RETURN VALUE: None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 #define F_INTH_RESET_ALL_IT { \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 * (volatile SYS_UWORD16 *) C_INTH_IT_REG1 &= 0x0000; \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 * (volatile SYS_UWORD16 *) C_INTH_IT_REG2 &= 0x0000; \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 * (volatile SYS_UWORD16 *) C_INTH2_IT_REG1 &= 0x0000; \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 * MACRO NAME: F_INTH_RESET_ONE_IT
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308 * Reset the interrupt specified in argument.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311 * ARGUMENT LIST:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 * Argument Description
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 * ------------ ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 * d_it Interrupt index
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 * RETURN VALUE: None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 #define F_INTH_RESET_ONE_IT(d_it) { \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 if (d_it < 16) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 * (volatile SYS_UWORD16 *) C_INTH_IT_REG1 &= ~(1 << d_it); \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 else if (d_it < C_INTH_NUM_INT) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325 * (volatile SYS_UWORD16 *) C_INTH_IT_REG2 &= ~(1 << (d_it-16)); \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 else if (d_it < (C_INTH_NUM_INT + C_INTH_2ND_NUM_INT)) \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327 * (volatile SYS_UWORD16 *) C_INTH2_IT_REG1 &= ~(1 << (d_it-32)); \
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 * MACRO NAME: F_INTH_VALID_NEXT
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 * Valid next interrupt on the main interrupt handler.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 * ARGUMENT LIST:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 * Argument Description
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339 * ------------ ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 * d_fiq_nirq Source of the interrupt IRQ or FIQ
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 * RETURN VALUE: None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 #define F_INTH_VALID_NEXT(d_fiq_nirq) * (volatile SYS_UWORD16 *) C_INTH_CTRL_REG |= (1 << d_fiq_nirq)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 * MACRO NAME: F_INTH2_VALID_NEXT
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 * Valid next interrupt on the 2nd level interrupt handler.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 * ARGUMENT LIST:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 * Argument Description
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359 * ------------ ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 * d_fiq_nirq Source of the interrupt IRQ or FIQ.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 * RETURN VALUE: None
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366 #define F_INTH2_VALID_NEXT(d_fiq_nirq) * (volatile SYS_UWORD16 *) C_INTH2_CTRL_REG |= (1 << d_fiq_nirq)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 * MACRO NAME: F_INTH_GET_IRQ
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 * Return pending IRQ interrupt index on the main interrupt handler.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 * ARGUMENT LIST:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 * Argument Description
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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379 * ------------ ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 * RETURN VALUE: IRQ interrupt index
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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382 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 #define F_INTH_GET_IRQ ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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389 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 * MACRO NAME: F_INTH_GET_FIQ
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 * Return pending FIQ interrupt index on the main interrupt handler.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 * ARGUMENT LIST:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397 * Argument Description
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 * ------------ ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400 * RETURN VALUE: FIQ interrupt index
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 #define F_INTH_GET_FIQ ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 * MACRO NAME: F_INTH2_GET_IRQ
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 * Return pending IRQ interrupt index on the 2nd level interrupt handler.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 * ARGUMENT LIST:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416 * Argument Description
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 * ------------ ----------------------------------------------------------
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 * RETURN VALUE: FIQ interrupt index
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 *
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 #define F_INTH2_GET_IRQ ((* (SYS_UWORD16 *) C_INTH2_B_IRQ_REG) & C_INTH2_SRC_NUM)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428 * STRUCTURE DEFINITION
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 typedef struct {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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432 SYS_UWORD8 d_fiq_nirq;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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433 SYS_UWORD8 d_edge_nlevel;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 SYS_UWORD8 d_priority;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 SYS_FUNC d_it_handler;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 } T_INTH_CONFIG;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 * GLOBAL VARIABLES REFERENCE
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444 extern SYS_FUNC a_inth_it_handlers[C_INTH_NUM_INT][2];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 extern SYS_FUNC a_inth2_irq_handlers[C_INTH_2ND_NUM_INT];
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 /****************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449 * PROTOTYPE DEFINITION
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450 ***************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 * 16-BIS functions
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455 extern void f_inth_setup(T_INTH_CONFIG *p_inth_config);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 extern SYS_UWORD16 f_inth_get_version(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
457
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 * 32-BIS functions
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
460 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461 extern void f_inth_dummy(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462 extern void f_inth_irq_handler(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
463 extern void f_inth_fiq_handler(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 extern void f_inth_2nd_level_handler(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466 #endif /* __SYS_INTH_H__ */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 #endif /* (CHIPSET == 12) */