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comparison src/cs/system/Main/init.c @ 265:0aa748b6413a

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src/cs/system/Main/init.c: initial import from LoCosto source
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 05 Aug 2017 02:02:16 +0000
parents
children f62b71017afd
comparison
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264:3edeadec6804 265:0aa748b6413a
1 /*
2 * INIT.C
3 *
4 * This module allows to initialize the board:
5 * - wait states,
6 * - unmask selected interrupts,
7 * - initialize clock,
8 * - disable watchdog.
9 * Dummy functions used by the EVA3 library are defined.
10 */
11
12 /* Config Files */
13
14 #pragma DUPLICATE_FOR_INTERNAL_RAM_START
15
16 #ifndef PSP_FAILSAFE
17 #define PSP_FAILSAFE 0
18 #warn "PSP Failsafe Flag Not Defined in your Build, taking default"
19 #endif
20
21
22 #ifndef _WINDOWS
23 #include "l1sw.cfg"
24 #include "rf.cfg"
25 #include "chipset.cfg"
26 #include "board.cfg"
27 #include "swconfig.cfg"
28 #if (OP_L1_STANDALONE == 0)
29 #include "rv.cfg"
30 #include "sys.cfg"
31 #include "debug.cfg"
32 #ifdef BLUETOOTH_INCLUDED
33 #include "btemobile.cfg"
34 #endif
35 #ifdef BLUETOOTH
36 #include "bluetooth.cfg"
37 #endif
38 #endif
39
40 #if (OP_L1_STANDALONE == 0)
41 #include "rv/rv_defined_swe.h"
42 #endif
43 #endif
44
45 /* Include Files */
46 #include <assert.h>
47 #include <ctype.h>
48 #include <stdarg.h>
49 #include <stdlib.h>
50 #include <string.h>
51
52 #include "nucleus.h"
53
54 #include "sys_types.h"
55 #include "l1_types.h"
56 #include "l1_confg.h"
57 #include "l1_const.h"
58 #include "pin_config.h" // added for Init tuned to Power Management
59
60 #if TESTMODE
61 #include "l1tm_defty.h"
62 #endif // TESTMODE
63
64 #if (AUDIO_TASK == 1)
65 #include "l1audio_const.h"
66 #include "l1audio_cust.h"
67 #include "l1audio_defty.h"
68 #endif // AUDIO_TASK
69
70 #if (L1_GTT == 1)
71 #include "l1gtt_const.h"
72 #include "l1gtt_defty.h"
73 #endif
74
75 #if (L1_MP3 == 1)
76 #include "l1mp3_defty.h"
77 #endif
78
79 #if (L1_MIDI == 1)
80 #include "l1midi_defty.h"
81 #endif
82
83 #if (L1_AAC == 1)
84 #include "l1aac_defty.h"
85 #endif
86 #if (L1_DYN_DSP_DWNLD == 1)
87 #include "l1_dyn_dwl_defty.h"
88 #endif
89
90 #if (TRACE_TYPE == 4)
91 #include "l1_defty.h"
92 #endif
93
94
95 #if ((OP_L1_STANDALONE == 1) && (CODE_VERSION != SIMULATION) && (PSP_STANDALONE == 0))
96
97 #if (AUDIO_TASK == 1)
98 #include "l1audio_signa.h"
99 #include "l1audio_msgty.h"
100 #endif // AUDIO_TASK
101
102 #if (L1_GTT == 1)
103 #include "l1gtt_signa.h"
104 #include "l1gtt_msgty.h"
105 #endif
106
107 #include "l1_defty.h"
108 #include "cust_os.h"
109 #include "l1_msgty.h"
110 #include "nu_main.h"
111 #include "l1_varex.h"
112 #include "l1_proto.h"
113 #include "hw_debug.h"
114 #include "l1_trace.h"
115
116 #endif /* ((OP_L1_STANDALONE == 1) && (CODE_VERSION != SIMULATION) && (PSP_STANDALONE==0)) */
117
118
119 #include "armio/armio.h"
120 #include "timer/timer.h"
121
122 #if (CHIPSET==15)
123 #include "types.h"
124 #include "bspI2c.h"
125 #include "bspTwl3029.h"
126 #include "bspTwl3029_I2c.h"
127 #include "bspTwl3029_Power.h"
128 #if (OP_L1_STANDALONE == 0)
129 #include "uicc/board/bspUicc.h"
130 #endif
131 #endif
132
133 #if (OP_L1_STANDALONE == 0)
134 #include "rvf/rvf_api.h"
135 #include "rvm/rvm_api.h" /* A-M-E-N-D-E-D! */
136 #include "sim/sim.h"
137 #endif
138
139 #include "dynamic_clock.h"
140 #if (ANLG_FAM !=11)
141 #include "abb/abb.h"
142 #endif
143
144 #if (BOARD==35 || BOARD==46)
145 #if (OP_L1_STANDALONE == 0)
146 #include "csmi/csmi.h"
147 #include "csmi/csmi_gsmctrl.h"
148 #include "csmi/csmi_uart.h"
149 #include "uart/uartfax.h"
150 #include "csmi/csmi_uartfax.h"
151 #include "ffs/ffs.h"
152 #include "ffs/ffspcm.h"
153 #include "csmi/sleep.h"
154 #endif /* (OP_L1_STANDALONE == 0) */
155 #endif
156
157 /* WCP Profiler */
158 #if (BOARD==35 || BOARD==43 || BOARD==46) && (OP_L1_STANDALONE == 0)
159 #if WCP_PROF == 1
160 #include "prf/prf_api.h"
161 #endif
162 #endif
163
164 #include "inth/iq.h"
165 #include "tpudrv.h"
166 #include "memif/mem.h"
167 #include "clkm/clkm.h"
168 #include "inth/inth.h"
169
170 #if (OP_L1_STANDALONE == 0)
171 void bspUicc_Phy_intCHandler(void);
172 #endif
173
174 #if (OP_L1_STANDALONE == 1)
175 #include "uart/serialswitch_core.h"
176 #else
177 #include "uart/serialswitch.h"
178 #endif
179 #include "uart/traceswitch.h"
180
181
182 #include "dma/dma.h"
183 #include "rhea/rhea_arm.h"
184
185 #include "ulpd/ulpd.h"
186
187 #if (PSP_STANDALONE == 0)
188 #if (GSM_IDLE_RAM != 0)
189 #if (OP_L1_STANDALONE == 1)
190 #include "csmi_simul.h"
191 #else
192 #include "csmi/csmi.h"
193 #endif
194 #endif
195 #endif
196
197 #if (CHIPSET == 12) || (CHIPSET == 15) || ((CHIPSET == 10) && (OP_WCP == 1))
198 #include "memif/sys_memif.h"
199 #endif
200
201 #if ((CHIPSET == 12) || (CHIPSET == 15))
202 #include "timer/timer_sec.h"
203 #include "dma/sys_dma.h"
204 #include "conf/sys_conf.h"
205 #include "inth/sys_inth.h"
206 #ifdef RVM_NAN_SWE
207 #include "nan/nan_i.h"
208 #endif
209 #ifdef RVM_DMA_SWE
210 #include "dma/board/dma_inth.h"
211 #endif
212 #ifdef RVM_I2C_SWE
213 #include "i2c/i2c_hw_functions.h"
214 #endif
215 #ifdef RVM_MC_SWE
216 #include "mc/board/mc_inth.h"
217 #endif
218 #ifdef RVM_USB_SWE
219 #include "usb/usb_inth.h"
220 #endif
221 #endif
222
223 #if (OP_L1_STANDALONE == 0)
224 #define TIMER_RESET_VALUE (0xFFFF)
225
226 /*
227 * These constants define the number of ticks per TDMA when timer 0
228 * is set to pre-scale=0 and the upper limit in percent of TICKS_PER_TDMA
229 * for the execution of synchronous layer 1.
230 */
231 #define TICKS_PER_TDMA (1875)
232 #define LIMIT_FOR_L1_SYNC (80)
233 #endif
234
235 UWORD16 flash_device_id;
236 #if (PSP_STANDALONE == 0)
237 #if (OP_L1_STANDALONE == 0)
238 extern void ffs_main_init(void);
239 extern void create_tasks(void);
240 #if TI_NUC_MONITOR == 1
241 extern void ti_nuc_monitor_tdma_action( void );
242 #endif
243
244 #if WCP_PROF == 1
245 #if PRF_CALIBRATION == 1
246 extern NU_HISR prf_CalibrationHISR;
247 #endif
248 #endif
249
250 #else
251 void l1ctl_pgm_clk32(UWORD32 nb_hf, UWORD32 nb_32khz);
252 extern void L1_trace_string(char *s);
253 #endif /* (OP_L1_STANDALONE) */
254 #endif
255
256 #if (CHIPSET == 12) || (CHIPSET == 15)
257 extern const T_INTH_CONFIG a_inth_config[C_INTH_NB_INTERRUPT];
258 #ifdef RVM_CAMD_SWE
259 extern void f_camera_interrupt_manager(void);
260 #endif
261 #endif
262
263 #if (GSM_IDLE_RAM != 0)
264 #if (CHIPSET == 12) || (CHIPSET == 15)
265
266 // Interrupt handler called in case the interrupt requires the traffic controler active
267 // These routines need to be declared here in order to put them into the a_inth_config_idle_ram structure
268 extern void ext_ram_irq_inth_handler(void);
269 extern void ext_ram_fiq_inth_handler(void);
270
271
272
273 // declared for the _intram file generated by ICL470
274 extern const T_INTH_CONFIG a_inth_config_idle_ram[C_INTH_NB_INTERRUPT];
275
276 // Debug mode: irq ext shall be connected to the chipselect signals
277 #if GSM_IDLE_RAM_DEBUG
278 extern void flash_access_handler(void);
279 extern void ext_ram_access_handler(void);
280 #endif
281 #endif // CHIPSET 12 || CHIPSET 15
282 #endif
283
284 #if (PSP_STANDALONE == 0)
285 extern void hisr(void);
286 extern void layer_1_sync_HISR_entry(void);
287
288 extern NU_HISR layer_1_sync_HISR;
289
290 #if (CODE_VERSION != SIMULATION)
291 #if (BOARD == 71)
292 extern void INT_DisableIRQ(void);
293 extern void INT_EnableIRQ(void);
294 #endif /* (BOARD == 71) */
295 #endif /* CODE_VERSION != SIMULATION */
296
297 #if (LOCOSTO_LITE==1)
298 #ifndef HISR_STACK_SHARING
299 #define HISR_STACK_SHARING
300 #endif
301 #endif
302
303 #ifdef HISR_STACK_SHARING
304 unsigned char HISR_STACK_PRIO2[1500]={0xFE};
305 #endif
306
307 #if (OP_L1_STANDALONE == 0)
308 #pragma DATA_SECTION(layer_1_sync_stack,".stackandheap");
309 #define LAYER_1_SYNC_STACK_SIZE (3000 /*4000*/)
310 extern unsigned char layer_1_sync_stack[LAYER_1_SYNC_STACK_SIZE];
311 #else
312 #if (LONG_JUMP == 3)
313 #pragma DATA_SECTION(layer_1_sync_stack,".HISR_stack");
314 #endif
315
316 #if TESTMODE
317 extern char FAR layer_1_sync_stack[2600 /*3600*/]; // Frame interrupt task stack for EVA3
318 #else
319 extern char FAR layer_1_sync_stack[1600 /*2600*/]; // Frame interrupt task stack for EVA3
320 #endif
321 #endif /* OP_L1_STANDALONE */
322
323 #if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1)
324 extern void api_modem_hisr();
325 #if (LONG_JUMP == 3)
326 #pragma DATA_SECTION(API_MODEM_HISR_stack,".l1s_global");
327 #endif
328 extern char FAR API_MODEM_HISR_stack[0x400]; // stack size to be tuned
329 extern NU_HISR api_modemHISR;
330 #endif
331
332 #pragma DUPLICATE_FOR_INTERNAL_RAM_END
333
334 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0))
335 #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START
336 #if (OP_L1_STANDALONE == 0)
337 /*
338 * Timing monitor
339 *
340 *
341 */
342 #if (TRACE_TYPE == 4)
343 extern T_L1A_L1S_COM l1a_l1s_com;
344 extern T_L1S_GLOBAL l1s;
345 UNSIGNED max_cpu, fn_max_cpu;
346 unsigned short layer_1_sync_end_time;
347 unsigned short max_cpu_flag;
348 #endif
349 #endif
350 #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
351 #endif // !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0))
352
353 #if (L1_EXT_AUDIO_MGT == 1)
354 NU_HISR EXT_AUDIO_MGT_hisr;
355 #ifndef HISR_STACK_SHARING
356 char FAR ext_audio_mgt_hisr_stack[500];
357 #else
358 #define ext_audio_mgt_hisr_stack HISR_STACK_PRIO2
359 #endif
360 extern void Cust_ext_audio_mgt_hisr(void);
361 #endif
362
363 #if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) ) // equivalent to an API_HISR flag
364 extern void api_hisr(void);
365 #ifndef HISR_STACK_SHARING
366 #if (LONG_JUMP == 3)
367 #pragma DATA_SECTION (API_HISR_stack,".l1s_global");
368 #endif
369
370 char FAR API_HISR_stack[0x400];
371 #else
372 #define API_HISR_stack HISR_STACK_PRIO2
373 #endif
374 NU_HISR apiHISR;
375 #endif // (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_DYN_DSP_DWNLD == 1)
376
377 #if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1)
378 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM != 0))
379 #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START
380 char FAR API_MODEM_HISR_stack[0x400]; // stack size to be tuned
381 NU_HISR api_modemHISR;
382 #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
383 #endif
384 #endif // FF_L1_IT_DSP_USF
385 #endif /* PSP_STANDALONE == 0 */
386
387 #if (OP_L1_STANDALONE == 1)
388 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) || TESTMODE)
389 #include "uart/uart.h"
390 /*
391 * Serial Configuration set up.
392 */
393
394 extern char ser_cfg_info[NUMBER_OF_TR_UART];
395 #include "rvt_gen.h"
396 extern T_RVT_USER_ID trace_id;
397 #endif
398 #endif /* (OP_L1_STANDALONE == 1) */
399
400 /*
401 * Serial Configuration set up.
402 */
403
404 /*
405 ** One config is:
406 ** {XXX_BT_HCI, // Bluetooth HCI
407 ** XXX_FAX_DATA, // Fax/Data AT-Cmd
408 ** XXX_TRACE, // L1/Riviera Trace Mux
409 ** XXX_TRACE}, // Trace PS
410 **
411 ** with XXX being DUMMY, UART_IRDA or UART_MODEM
412 */
413
414 #if ((((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) ||\
415 (TESTMODE)) && (OP_L1_STANDALONE == 1)) || (OP_L1_STANDALONE == 0))
416 #if (OP_L1_STANDALONE == 1)
417 static T_AppliSerialInfo appli_ser_cfg_info =
418 #else
419 T_AppliSerialInfo appli_ser_cfg_info =
420 #endif /* OP_L1_STANDALONE */
421 #if (CHIPSET!=15)
422 {
423 #ifdef BTEMOBILE
424 #ifdef BT_UART_USED_MODEM
425 {UART_MODEM_BT_HCI,
426 DUMMY_FAX_DATA,
427 UART_IRDA_TRACE,
428 DUMMY_TRACE}, // default config (Bluetooth on Modem) - 0x014A
429 #else
430 {UART_IRDA_TRACE,
431 DUMMY_FAX_DATA,
432 UART_MODEM_TRACE,
433 DUMMY_TRACE}, // default config (Bluetooth on IrDa) - 0x0249
434 #endif // BT_UART_USED_MODEM
435 #else // BTEMOBILE
436 {DUMMY_BT_HCI,
437 UART_MODEM_FAX_DATA,
438 UART_IRDA_TRACE,
439 DUMMY_TRACE}, // default config = 0x0168
440 #endif
441 #ifdef BTEMOBILE
442 12, // 12 serial config allowed
443 #else // BTEMOBILE
444 9, // 9 serial config allowed
445 #endif
446 {
447 // Configs with Condat Panel only
448 {DUMMY_BT_HCI,
449 DUMMY_FAX_DATA,
450 DUMMY_TRACE,
451 UART_IRDA_TRACE}, // 0x1048
452 {DUMMY_BT_HCI,
453 DUMMY_FAX_DATA,
454 DUMMY_TRACE,
455 UART_MODEM_TRACE}, // 0x2048
456 // Configs with L1/Riviera Trace only
457 {DUMMY_BT_HCI,
458 DUMMY_FAX_DATA,
459 UART_IRDA_TRACE,
460 DUMMY_TRACE}, // 0x0148
461 {DUMMY_BT_HCI,
462 DUMMY_FAX_DATA,
463 UART_MODEM_TRACE,
464 DUMMY_TRACE}, // 0x0248
465 // Configs with AT-Cmd only
466 {DUMMY_BT_HCI,
467 UART_MODEM_FAX_DATA,
468 DUMMY_TRACE,
469 DUMMY_TRACE}, // 0x0068
470 // Configs with Condat Panel and L1/Riviera Trace
471 {DUMMY_BT_HCI,
472 DUMMY_FAX_DATA,
473 UART_MODEM_TRACE,
474 UART_IRDA_TRACE}, // 0x1248
475 {DUMMY_BT_HCI,
476 DUMMY_FAX_DATA,
477 UART_IRDA_TRACE,
478 UART_MODEM_TRACE}, // 0x2148
479 // Configs with Condat Panel and AT-Cmd
480 {DUMMY_BT_HCI,
481 UART_MODEM_FAX_DATA,
482 DUMMY_TRACE,
483 UART_IRDA_TRACE}, // 0x1068
484 #ifdef BTEMOBILE
485 // Configs with L1/Riviera Trace and Bluetooth HCI
486 {UART_IRDA_BT_HCI,
487 DUMMY_FAX_DATA,
488 UART_MODEM_TRACE,
489 DUMMY_TRACE}, // 0x0249
490 {UART_MODEM_BT_HCI,
491 DUMMY_FAX_DATA,
492 UART_IRDA_TRACE,
493 DUMMY_TRACE}, // 0x014A
494 // Configs with AT-Cmd and Bluetooth HCI
495 {UART_IRDA_BT_HCI,
496 UART_MODEM_FAX_DATA,
497 DUMMY_TRACE,
498 DUMMY_TRACE}, // 0x0069
499 #endif // BTEMOBILE
500 // Configs with L1/Riviera Trace and AT-Cmd
501 {DUMMY_BT_HCI,
502 UART_MODEM_FAX_DATA,
503 UART_IRDA_TRACE,
504 DUMMY_TRACE} // 0x0168
505 }
506 };
507 #else /* CHIPSET==15 */
508 {
509 {DUMMY_BT_HCI,
510 DUMMY_FAX_DATA,
511 UART_IRDA_TRACE,
512 DUMMY_TRACE}, // 0x0148
513 3,
514 {
515 {DUMMY_BT_HCI,
516 DUMMY_FAX_DATA,
517 UART_IRDA_TRACE,
518 DUMMY_TRACE},// 0x0148
519 {DUMMY_BT_HCI,
520 DUMMY_FAX_DATA,
521 DUMMY_TRACE,
522 UART_IRDA_TRACE}, // 0x1048
523 {UART_IRDA_BT_HCI,
524 DUMMY_FAX_DATA,
525 DUMMY_TRACE,
526 DUMMY_TRACE}, // 0x0049
527 }
528 };
529 #endif /* CHIPSET !=15*/
530 #endif /* (TRACE_TYPE ...) || (OP_L1_STANDALONE == 0) */
531
532
533 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0))
534 #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START
535
536 #if (PSP_STANDALONE == 0)
537 /*
538 * HISR stack and semaphore needed by L1
539 */
540
541 #if (OP_L1_STANDALONE == 0)
542 unsigned char layer_1_sync_stack[LAYER_1_SYNC_STACK_SIZE];
543 #else
544 #if TESTMODE
545 char FAR layer_1_sync_stack[2600 /*3600*/]; // Frame interrupt task stack for EVA3
546 #else
547 char FAR layer_1_sync_stack[1600 /* 2600 */]; // Frame interrupt task stack for EVA3
548 #endif
549 #endif /* OP_L1_STANDALONE */
550
551 NU_HISR layer_1_sync_HISR; // Frame interrupt task stack for EVA3
552 #endif
553
554 #if (CHIPSET == 12)
555
556 const T_INTH_CONFIG a_inth_config[C_INTH_NB_INTERRUPT] =
557 { // IRQ/FIQ LEVEL/EDGE PRIORITY HANDLER
558 { C_INTH_IRQ, C_INTH_EDGE, 0x01, IQ_TimerHandler }, // 0 : WATCHDOG TIMER
559 { C_INTH_IRQ, C_INTH_EDGE, 0x02, IQ_TimerHandler1 }, // 1 : TIMER 1
560 { C_INTH_IRQ, C_INTH_EDGE, 0x02, IQ_TimerHandler2 }, // 2 : TIMER 2
561 { C_INTH_FIQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 3 : TSP RECEIVE
562 { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_FrameHandler }, // 4 : TPU FRAME
563 { C_INTH_IRQ, C_INTH_EDGE, 0x04, f_inth_dummy }, // 5 : TPU PAGE
564 #if (OP_L1_STANDALONE == 1)
565 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 6 : SIM
566 #else
567 { C_INTH_IRQ, C_INTH_EDGE, 0x07, SIM_IntHandler }, // 6 : SIM
568 #endif
569 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, SER_uart_modem_handler }, // 7 : UART_MODEM1
570 #if (OP_L1_STANDALONE == 1)
571 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, f_inth_dummy }, // 8 : KEYBOARD
572 #else
573 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, IQ_KeypadHandler }, // 8 : KEYBOARD
574 #endif
575 { C_INTH_IRQ, C_INTH_EDGE, 0x03, IQ_Rtc_Handler }, // 9 : RTC_TIMER
576 { C_INTH_IRQ, C_INTH_LEVEL, 0x03, IQ_RtcA_Handler }, // 10 : RTC_ALARM
577 { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_Gauging_Handler }, // 11 : ULPD_GAUGING
578 { C_INTH_IRQ, C_INTH_EDGE, 0x08, IQ_External }, // 12 : ABB_IRQ
579 { C_INTH_IRQ, C_INTH_EDGE, 0x05, f_inth_dummy }, // 13 : SPI
580 { C_INTH_IRQ, C_INTH_LEVEL, 0x06, f_dma_interrupt_manager }, // 14 : DMA
581 { C_INTH_IRQ, C_INTH_EDGE, 0x03, IQ_ApiHandler }, // 15 : API
582 { C_INTH_IRQ, C_INTH_EDGE, 0x07, f_inth_dummy }, // 16 : GPIO
583 { C_INTH_FIQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 17 : ABB_FIQ
584 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, SER_uart_irda_handler }, // 18 : UART_IRDA
585 { C_INTH_IRQ, C_INTH_LEVEL, 0x03, IQ_GsmTim_Handler }, // 19 : ULPD GSM TIMER
586 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 20 : GEA
587 #if GSM_IDLE_RAM_DEBUG
588 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, flash_access_handler }, // 21 : EXTERNAL IRQ 1
589 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_access_handler }, // 22 : EXTERNAL IRQ 2
590 #else
591 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 21 : EXTERNAL IRQ 1
592 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 22 : EXTERNAL IRQ 2
593 #endif
594 #if (OP_L1_STANDALONE == 0)
595 { C_INTH_FIQ, C_INTH_LEVEL, 0x02, bspUicc_Phy_intCHandler }, // 23 : USIM Card Detect
596 { C_INTH_IRQ, C_INTH_EDGE, 0x02, bspUicc_Phy_intCHandler }, // 24 : USIM
597 #else
598 { C_INTH_FIQ, C_INTH_LEVEL, 0x02, f_inth_dummy }, // 23 : USIM Card Detect
599 { C_INTH_IRQ, C_INTH_EDGE, 0x02, f_inth_dummy }, // 24 : USIM
600 #endif
601 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 25 : LCD
602 #if (OP_L1_STANDALONE == 1)
603 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 26 : USB
604 #else
605 #ifdef RVM_USB_SWE
606 { C_INTH_IRQ, C_INTH_LEVEL, 0x00, usb_int_handler }, // 26 : USB
607 #else
608 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy },
609 #endif
610 #endif
611 #if (OP_L1_STANDALONE == 1)
612 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 27 : MMC/SD/MS
613 #else
614 #ifdef RVM_MC_SWE
615 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, mc_int_handler }, // 27 : MMC/SD/MS
616 #else
617 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy },
618 #endif
619 #endif
620 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, SER_uart_modem2_handler }, // 28 : UART_MODEM2
621 #if (OP_L1_STANDALONE == 1)
622 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_2nd_level_handler }, // 29 : 2nd Interrupt Handler
623 #else
624 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, f_inth_2nd_level_handler }, // 29 : 2nd Interrupt Handler
625 #endif
626 #if (OP_L1_STANDALONE == 1)
627 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 30 : I2C
628 #else
629 #ifdef RVM_I2C_SWE
630 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, i2c_hw_int_manager }, // 30 : I2C
631 #else
632 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy },
633 #endif
634 #endif
635 #if (OP_L1_STANDALONE == 1)
636 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 31 : NAND FLASH
637 #else
638 #ifdef RVM_NAN_SWE
639 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, nan_IT_handler }, // 31 : NAND FLASH
640 #else
641 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy },
642 #endif
643 #endif
644
645 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 0 : RNG
646 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 1 : SHA1/MD5
647 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 2 : EMPU
648 { C_INTH_IRQ, C_INTH_LEVEL, 0x06, f_dma_interrupt_manager }, // 14 : DMA
649 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy } // 4 : Secure TIMER
650 };
651
652 #if (GSM_IDLE_RAM != 0)
653 const T_INTH_CONFIG a_inth_config_idle_ram[C_INTH_NB_INTERRUPT] =
654 { // IRQ/FIQ LEVEL/EDGE PRIORITY HANDLER
655 { C_INTH_IRQ, C_INTH_EDGE, 0x01, ext_ram_irq_inth_handler }, // 0 : WATCHDOG TIMER
656 { C_INTH_IRQ, C_INTH_EDGE, 0x02, ext_ram_irq_inth_handler }, // 1 : TIMER 1
657 { C_INTH_IRQ, C_INTH_EDGE, 0x02, ext_ram_irq_inth_handler }, // 2 : TIMER 2
658 { C_INTH_FIQ, C_INTH_EDGE, 0xFF, ext_ram_fiq_inth_handler }, // 3 : TSP RECEIVE
659 { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_FrameHandler }, // 4 : TPU FRAME
660 { C_INTH_IRQ, C_INTH_EDGE, 0x04, ext_ram_irq_inth_handler }, // 5 : TPU PAGE
661 #if (OP_L1_STANDALONE == 1)
662 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, ext_ram_irq_inth_handler }, // 6 : SIM
663 #else
664 { C_INTH_IRQ, C_INTH_EDGE, 0x07, ext_ram_irq_inth_handler }, // 6 : SIM
665 #endif
666 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, ext_ram_irq_inth_handler }, // 7 : UART_MODEM1
667 #if (OP_L1_STANDALONE == 1)
668 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_irq_inth_handler }, // 8 : KEYBOARD
669 #else
670 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_irq_inth_handler }, // 8 : KEYBOARD
671 #endif
672 { C_INTH_IRQ, C_INTH_EDGE, 0x03, ext_ram_irq_inth_handler }, // 9 : RTC_TIMER
673 { C_INTH_IRQ, C_INTH_LEVEL, 0x03, ext_ram_irq_inth_handler }, // 10 : RTC_ALARM
674 { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_Gauging_Handler }, // 11 : ULPD_GAUGING
675 { C_INTH_IRQ, C_INTH_EDGE, 0x08, ext_ram_irq_inth_handler }, // 12 : ABB_IRQ
676 { C_INTH_IRQ, C_INTH_EDGE, 0x05, ext_ram_irq_inth_handler }, // 13 : SPI
677 #if (OP_L1_STANDALONE == 1)
678 { C_INTH_IRQ, C_INTH_LEVEL, 0x06, ext_ram_irq_inth_handler }, // 14 : DMA
679 #else
680 { C_INTH_IRQ, C_INTH_EDGE, 0x02, ext_ram_irq_inth_handler }, // 14 : DMA
681 #endif
682 { C_INTH_IRQ, C_INTH_EDGE, 0x03, ext_ram_irq_inth_handler }, // 15 : API
683 { C_INTH_IRQ, C_INTH_EDGE, 0x07, ext_ram_irq_inth_handler }, // 16 : GPIO
684 { C_INTH_FIQ, C_INTH_EDGE, 0xFF, ext_ram_fiq_inth_handler }, // 17 : ABB_FIQ
685 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, ext_ram_irq_inth_handler }, // 18 : UART_IRDA
686 { C_INTH_IRQ, C_INTH_LEVEL, 0x03, IQ_GsmTim_Handler }, // 19 : ULPD GSM TIMER
687 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 20 : GEA
688 #if GSM_IDLE_RAM_DEBUG
689 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, flash_access_handler }, // 21 : EXTERNAL IRQ 1
690 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_access_handler }, // 22 : EXTERNAL IRQ 2
691 #else
692 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 21 : EXTERNAL IRQ 1
693 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 22 : EXTERNAL IRQ 2
694 #endif
695 { C_INTH_FIQ, C_INTH_LEVEL, 0xFF, ext_ram_fiq_inth_handler }, // 23 : USIM Card Detect
696 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, ext_ram_irq_inth_handler }, // 24 : USIM
697 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 25 : LCD
698 #if (OP_L1_STANDALONE == 1)
699 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 26 : USB
700 #else
701 { C_INTH_IRQ, C_INTH_LEVEL, 0x00, ext_ram_irq_inth_handler }, // 26 : USB
702 #endif
703 #if (OP_L1_STANDALONE == 1)
704 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 27 : MMC/SD/MS
705 #else
706 #ifdef RVM_MC_SWE
707 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_irq_inth_handler }, // 27 : MMC/SD/MS
708 #else
709 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, ext_ram_irq_inth_handler },
710 #endif
711 #endif
712 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, ext_ram_irq_inth_handler }, // 28 : UART_MODEM2
713 #if (OP_L1_STANDALONE == 1)
714 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 29 : 2nd Interrupt Handler
715 #else
716 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, ext_ram_irq_inth_handler }, // 29 : 2nd Interrupt Handler
717 #endif
718 #if (OP_L1_STANDALONE == 1)
719 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 30 : I2C
720 #else
721 { C_INTH_IRQ, C_INTH_EDGE, 0x01, ext_ram_irq_inth_handler }, // 30 : I2C
722 #endif
723 #if (OP_L1_STANDALONE == 1)
724 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 31 : NAND FLASH
725 #else
726 { C_INTH_IRQ, C_INTH_EDGE, 0x02, ext_ram_irq_inth_handler }, // 31 : NAND FLASH
727 #endif
728
729 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 0 : RNG
730 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 1 : SHA1/MD5
731 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 2 : EMPU
732 #if (OP_L1_STANDALONE == 1)
733 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 3 : Secure DMA
734 #else
735 { C_INTH_IRQ, C_INTH_LEVEL,  0x03,   ext_ram_irq_inth_handler  }, // 3  : Secure DMA
736 #endif
737 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler } // 4 : Secure TIMER
738 };
739 #endif //(GSM_IDLE_RAM != 0)
740
741 #endif /* (CHIPSET ==12) */
742
743 #if (CHIPSET == 15)
744 const T_INTH_CONFIG a_inth_config[C_INTH_NB_INTERRUPT] =
745 { // IRQ/FIQ LEVEL/EDGE PRIORITY HANDLER
746 { C_INTH_IRQ, C_INTH_EDGE, 0x01, IQ_TimerHandler }, // 0 : WATCHDOG TIMER
747 { C_INTH_IRQ, C_INTH_EDGE, 0x02, IQ_TimerHandler1 }, // 1 : TIMER 1
748 { C_INTH_IRQ, C_INTH_EDGE, 0x02, IQ_TimerHandler2 }, // 2 : TIMER 2
749 { C_INTH_FIQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 3 : MCSI
750 #if (PSP_STANDALONE == 0)
751 { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_FrameHandler }, // 4 : TPU FRAME
752 #else
753 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 4 : TPU FRAME
754 #endif
755 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 5 : TPU PAGE
756 #if (OP_L1_STANDALONE == 1)
757 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 6 : DRP DBB
758 #else
759 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 6 : DRP DBB
760 #endif
761 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, SER_uart_irda_handler }, // 7 : UART_IRDA
762 #if (OP_L1_STANDALONE == 1)
763 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 8 : KEYBOARD
764 #else
765 { C_INTH_IRQ, C_INTH_LEVEL, 0x01, IQ_KeypadHandler }, // 8 : KEYBOARD
766 #endif
767 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 9 : DRP DBB RX
768
769 #ifdef RVM_CAMD_SWE
770
771 { C_INTH_IRQ, C_INTH_LEVEL, 0x03, f_camera_interrupt_manager }, // 10 : CAMERA
772
773 #else
774 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 10 : CAMERA
775
776 #endif
777
778 #if (PSP_STANDALONE == 0)
779 { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_Gauging_Handler }, // 11 : ULPD_GAUGING
780 #else
781 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 11 : ULPD_GAUGING
782 #endif
783 { C_INTH_IRQ, C_INTH_EDGE, 0x08, IQ_External }, // 12 : ABB_IRQ
784 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 13 : MSSPI
785 { C_INTH_IRQ, C_INTH_LEVEL, 0x06, f_dma_interrupt_manager }, // 14 : DMA
786 #if (PSP_STANDALONE == 0)
787 { C_INTH_IRQ, C_INTH_EDGE, 0x03, IQ_ApiHandler }, // 15 : API
788 #else
789 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 15 : API
790 #endif
791 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 16 : GPIO
792 { C_INTH_FIQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 17 : ABB_FIQ
793 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 18 : DRP DBB RX
794 #if (PSP_STANDALONE == 0)
795 { C_INTH_IRQ, C_INTH_LEVEL, 0x03, IQ_GsmTim_Handler }, // 19 : ULPD GSM TIMER
796 #else
797 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 19 : ULPD GSM TIMER
798 #endif
799 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 20 : GEA
800 #if GSM_IDLE_RAM_DEBUG
801 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 21 : GPIO1
802 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 22 : GPIO2
803 #else
804 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 21 : GPIO1
805 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 22 : GPIO2
806 #endif
807 { C_INTH_FIQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 23 : CPORT
808 #if(OP_L1_STANDALONE == 1)
809 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 24 : USIM
810 #else
811 { C_INTH_IRQ, C_INTH_EDGE, 0x04, bspUicc_Phy_intCHandler }, // 24 : USIM
812 #endif
813 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 25 : LCD
814 #if (OP_L1_STANDALONE == 1)
815 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 26 : USB
816 #else
817 #ifdef RVM_USB_SWE
818 { C_INTH_IRQ, C_INTH_LEVEL, 0x03, usb_int_handler }, // 26 : USB
819 #else
820 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy },
821 #endif
822 #endif
823 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 27 : not used
824 { C_INTH_IRQ, C_INTH_LEVEL, 0x03, bspI2c_Handeler2 }, // 28 : I2C TRITON
825 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, f_inth_2nd_level_handler }, // 29 : 2nd Interrupt Handler
826 { C_INTH_IRQ, C_INTH_LEVEL, 0x03, bspI2c_Handeler1 }, // 30 : I2C
827 #if (OP_L1_STANDALONE == 1)
828 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 31 : NAND FLASH
829 #else
830 #ifdef RVM_NAN_SWE
831 { C_INTH_IRQ, C_INTH_LEVEL, 0x02, nan_IT_handler }, // 31 : NAND FLASH
832 #else
833 { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy },
834 #endif
835 #endif
836
837 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 0 : RNG
838 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 1 : SHA1/MD5
839 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 2 : EMPU
840 { C_INTH_IRQ, C_INTH_LEVEL, 0x06, f_dma_interrupt_manager }, // 14 : DMA
841 { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy } // 4 : Secure TIMER
842 };
843 #endif /* CHIPSET == 15 */
844
845 #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
846 #endif // !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0))
847
848 #if (CHIPSET == 12)
849 const T_DMA_TYPE_GLOBAL_PARAMETER d_dma_global_parameter=
850 {
851 #if (CHIPSET_PG == CP_PG_F751685A)
852 C_DMA_AUTO_GATE_ON,
853 #else
854 C_DMA_AUTO_GATE_OFF,
855 #endif /* endif (CHIPSET_PG == F751685A) */
856 C_DMA_API_PRIO_ARM,
857 C_DMA_RHEA_PRIO_ARM,
858 C_DMA_IMIF_PRIO_CPU_4
859 };
860
861 #endif /* (CHIPSET ==12) */
862
863 #if (CHIPSET == 15)
864 const T_DMA_TYPE_GLOBAL_PARAMETER d_dma_global_parameter=
865 {
866 C_DMA_AUTO_GATE_ON,
867 C_DMA_API_PRIO_ARM,
868 C_DMA_RHEA_PRIO_ARM,
869 C_DMA_IMIF_PRIO_CPU_4,
870 C_DMA_IPERIF_PRIO_CPU_4, // set same as the IMIF priority. Actual value need to decided
871 C_DMA_EMIF_DMA_PRIO_7, // Actual value need to be decided
872 C_DMA_EMIF_MCU_PRIO_5 // Actual value need to be decided
873 };
874
875 #endif
876
877
878 #if (GSM_IDLE_RAM != 0)
879
880 #define IRQ_STACK_SIZE 128
881 #pragma DATA_SECTION(irq_stack,".irqstk");
882 UWORD32 irq_stack[IRQ_STACK_SIZE/4];
883 const UWORD32 irq_stack_size = IRQ_STACK_SIZE;
884
885 #define FIQ_STACK_SIZE 512
886 #pragma DATA_SECTION(fiq_stack,".fiqstk");
887 UWORD32 fiq_stack[FIQ_STACK_SIZE/4];
888 const UWORD32 fiq_stack_size = FIQ_STACK_SIZE;
889
890 #define SVC_STACK_SIZE 1024
891 #pragma DATA_SECTION(svc_stack,".svcstk");
892 UWORD32 svc_stack[SVC_STACK_SIZE/4];
893 const UWORD32 svc_stack_size = SVC_STACK_SIZE;
894
895 #define TIMER_HISR_STACK_SIZE 1024
896 #pragma DATA_SECTION(timer_hisr_stack,".timstk");
897 UWORD32 timer_hisr_stack[TIMER_HISR_STACK_SIZE/4];
898 const UWORD32 timer_hisr_stack_size = TIMER_HISR_STACK_SIZE;
899 #endif
900
901 /* HISR_STACK_SHARING: Create global stacks to be used by all HISRs
902 * having the same priority */
903
904
905
906 #if (CODE_VERSION != SIMULATION)
907 /*
908 * Init_Target
909 *
910 * Performs low-level HW Initialization.
911 */
912 void Init_Target(void)
913 {
914
915
916 #if (BOARD==70)|| (BOARD==71)
917 /* Variable for reading the BCR for MCP RAM */
918 unsigned short bcrTmpVal;
919 #endif
920 (*(volatile Uint16 *) 0xFFFF702A) = 0x0002;//reset the UART module.
921 #if (CHIPSET == 15)
922 char detect_code[80];
923 typedef void (*pf_t)(UWORD32, UWORD16 *, UWORD16 *);
924 extern void ffsdrv_device_id_read(UWORD32 base_addr, UWORD16 *manufact, UWORD16 *device);
925 pf_t myfp;
926 UWORD16 manufact;
927 UWORD16 device_id[3];
928
929 #endif
930 #if (BOARD == 5)
931 #define WS_ROM (1)
932 #define WS_RAM (1)
933 #define WS_APIF (1)
934 #define WS_CS2 (7) /* LCD on EVA3. */
935 #define WS_CS0 (7) /* DUART on EVA3. UART16750 and latch on A-Sample. */
936 #define WS_CS1 (7) /* LCD on A-Sample. */
937
938 IQ_InitWaitState (WS_ROM, WS_RAM, WS_APIF, WS_CS2, WS_CS0, WS_CS1);
939 IQ_InitClock (2); /* Internal clock division factor. */
940
941 IQ_MaskAll (); /* Mask all interrupts. */
942 IQ_SetupInterrupts (); /* IRQ priorities. */
943
944 TM_DisableWatchdog ();
945
946 /*
947 * Reset all TSP and DBG fdefault values
948 */
949
950 AI_ResetTspIO ();
951 AI_ResetDbgReg ();
952 AI_ResetIoConfig ();
953
954 /*
955 * Warning! The external reset signal is connected to the Omega and the
956 * external device. If the layer 1 is used its initialization removes
957 * the external reset. If the application does not use the layer 1
958 * you must remove the external reset (bit 2 of the reset control
959 * register 0x505808).
960 */
961
962 AI_ResetTspIO();
963 AI_ResetDbgReg();
964 AI_ResetIoConfig();
965
966 /*
967 * Configure all IOs (see RD300 specification).
968 */
969
970 AI_ConfigBitAsInput (1);
971 AI_EnableBit (1);
972
973 AI_ConfigBitAsOutput (2);
974 AI_EnableBit (2);
975
976 AI_ConfigBitAsInput (11);
977 AI_EnableBit (11);
978
979 AI_ConfigBitAsOutput (13);
980 AI_EnableBit (13);
981
982 AI_Power (1); /* Maintain power supply. */
983
984 #elif (BOARD == 6) || (BOARD == 7) || (BOARD == 8) || (BOARD == 9) || \
985 (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45) || \
986 (BOARD == 35) || (BOARD == 46) || (BOARD == 70) || (BOARD == 71)
987
988 #if (PSP_STANDALONE == 0)
989 // RIF/SPI rising edge clock for ULYSSE
990 //--------------------------------------------------
991 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)|| (ANLG_FAM == 11))
992 #if ((CHIPSET >= 3))
993 #if (CHIPSET == 12)
994 F_CONF_RIF_RX_RISING_EDGE;
995 F_CONF_SPI_RX_RISING_EDGE;
996 #elif (CHIPSET == 15)
997 //do the DRP init here for Locosto
998 #if (L1_DRP == 1)
999 // drp_power_on(); This should be done after the script is downloaded.
1000 #endif
1001 #else
1002 #if (BOARD==35)
1003 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000;
1004 #else
1005 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000;
1006 #endif /* (BOARD == 35) */
1007 #endif
1008 #endif
1009 #endif /* ANLG(ANALOG)) */
1010
1011 #if (OP_L1_STANDALONE == 1)
1012 #if (BOARD == 40) || (BOARD == 41) || \
1013 (BOARD == 42) || (BOARD == 43) || (BOARD == 45)
1014 // enable 8 Ohm amplifier for audio on D-sample
1015 AI_ConfigBitAsOutput (1);
1016 AI_SetBit(1);
1017 #elif (BOARD == 70) || (BOARD == 71)
1018 //Locosto I-sample or UPP costo board.BOARD
1019 // Initialize the ARMIO bits as per the I-sample spec
1020 // FIXME
1021 #endif
1022 #endif /* (OP_L1_STANDALONE == 1) */
1023 #endif /* PSP_STANDALONE ==0 */
1024
1025 // Watchdog
1026 //--------------------------------------------------
1027 TM_DisableWatchdog(); /* Disable Watchdog */
1028 #if (CHIPSET == 12) || (CHIPSET == 15)
1029 TM_SEC_DisableWatchdog();
1030 #endif
1031
1032 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
1033
1034 #if (CHIPSET == 12)
1035
1036 #if 0 /* example of configuration for DMA debug */
1037 #if (BOARD == 6) /* debug on EVA 4 , GPO2 must not be changed */
1038
1039 /* TPU_FRAME, NMIIT, IACKn */
1040 F_DBG_IRQ_CONFIG(C_DBG_IRQ_IRQ4|C_DBG_IRQ_NMIIT|C_DBG_IRQ_IACKN);
1041
1042 /* NDMA_REQ_VIEW1, NDMA_REQ_VIEW0, DMA_V(1), DMA_S(1), DMAREQ_P1(3:0)*/
1043 F_DBG_DMA_P1_NDFLASH_CONFIG(C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_1 |
1044 C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_0 |
1045 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_3 |
1046 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_2 |
1047 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_1 |
1048 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_0 |
1049 C_DBG_DMA_P1_NDFLASH_DMA_REQ_S_1 |
1050 C_DBG_DMA_P1_NDFLASH_DMA_REQ_V1 );
1051 /* DMA_REQ_S(2)*/
1052 F_DBG_DMA_P2_CONFIG(C_DBG_DMA_P2_DMA_REQ_S2);
1053
1054 /* DMA_CLK_REQ, BRIDGE_CLK */
1055 F_DBG_CLK1_CONFIG(C_DBG_CLK1_DMA_CLK_REQ |
1056 C_DBG_CLK1_BRIDGE_CLK );
1057
1058 /* XIO_nREADY */
1059 F_DBG_IMIF_CONFIG(C_DBG_IMIF_XIO_NREADY_MEM);
1060
1061 /* DSP_nIRQ_VIEW1, DSP_nIRQ_VIEW0, BRIDGE_EN */
1062 F_DBG_KB_USIM_SHD_CONFIG(C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_1 |
1063 C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_0 |
1064 C_DBG_KB_USIM_SHD_BRIDGE_EN );
1065
1066 /* RHEA_nREADY , RHEA_nSTROBE */
1067 F_DBG_USIM_CONFIG(C_DBG_USIM_RHEA_NSTROBE |
1068 C_DBG_USIM_RHEA_NREADY );
1069
1070 /* XIO_STROBE */
1071 F_DBG_MISC2_CONFIG(C_DBG_MISC2_X_IOSTRBN);
1072
1073 /* DMA_CLK_REQ */
1074 F_DBG_CLK2_CONFIG(C_DBG_CLK2_DMA_CLK_REQ2);
1075
1076 /* DSP_IRQ_SEL0=DMA, DSP_IRQ_SEL1=DMA, DMA_REQ_SEL0=RIF_RX, DMA_REQ_SEL1=RIF_RX */
1077 F_DBG_VIEW_CONFIG(0,0,C_DBG_DSP_INT_DMA,
1078 C_DBG_DSP_INT_DMA,
1079 C_DMA_CHANNEL_RIF_RX,
1080 C_DMA_CHANNEL_RIF_RX);
1081
1082 #endif /* (BOARD == 6) */
1083 #endif /* DMA debug example */
1084 #else
1085 /*
1086 * Configure ASIC in order to output the DPLL and ARM clock
1087 */
1088 // (*( volatile UWORD16* )(0xFFFEF008)) = 0x8000; // DPLL
1089 // (*( volatile UWORD16* )(0xFFFEF00E)) = 0x0004; // ARM clock
1090 // (*( volatile UWORD16* )(0xfffef004)) = 0x0600; // DSP clock + nIACK
1091 #endif /* (CHIPSET == 12) || CHIPSET == 15*/
1092
1093
1094 /*
1095 * Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules
1096 */
1097 // IRQ, Timer and bridge may SLEEP
1098 // In first step, same configuration as SAMSON
1099 //--------------------------------------------------
1100 #if (CHIPSET == 12)
1101 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_BRIDGE_DIS | CLKM_DPLL_DIS);
1102 #elif (CHIPSET == 15)
1103 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_CPORT_EN | CLKM_BRIDGE_DIS | 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/
1104
1105 #else
1106 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS);
1107
1108 // Select VTCXO input frequency
1109 //--------------------------------------------------
1110 CLKM_UNUSED_VTCXO_26MHZ;
1111
1112 // Rita RF uses 26MHz VCXO
1113 #if (RF_FAM == 12)
1114 CLKM_USE_VTCXO_26MHZ;
1115 #endif
1116 // Renesas RF uses 26MHz on F-sample but 13MHz on TEB
1117 #if (RF_FAM == 43) && (BOARD == 46)
1118 CLKM_USE_VTCXO_26MHZ;
1119 #endif
1120 #endif
1121
1122 #if (CHIPSET ==15)
1123 //Enable APLL
1124 *((volatile unsigned short *) (C_MAP_CLKM_BASE+0x10)) = 0x01|0x6;
1125 // UART Clock from APLL
1126 *((volatile unsigned short *) CLKM_CNTL_CLK_PROG_FREE_RUNN) = 0x0001;
1127 (*(volatile Uint16 *) 0xFFFF702A) = 0x0002;//reset the UART module.
1128
1129 #endif
1130
1131
1132
1133
1134 //
1135 // Control HOM/SAM automatic switching
1136 //--------------------------------------------------
1137 *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG;
1138
1139 /*
1140 * Disable and Clear all pending interrupts
1141 */
1142 #if (CHIPSET == 12) || (CHIPSET == 15)
1143 F_INTH_DISABLE_ALL_IT; // MASK all it
1144 F_INTH2_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH2 IRQ
1145 F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ
1146 F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ
1147 F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source
1148 #else
1149 INTH_DISABLEALLIT;
1150 INTH_RESETALLIT;
1151 INTH_CLEAR; /* reset IRQ/FIQ source */
1152 #endif
1153
1154 #if (CHIPSET == 12)
1155 /* API-RHEA control register configuration */
1156 f_memif_init_api_rhea_ctrl(C_MEMIF_API_RHEA_ADAPT,
1157 C_MEMIF_API_RHEA_ADAPT,
1158 C_MEMIF_API_RHEA_ADAPT,
1159 C_MEMIF_API_RHEA_NO_DEBUG);
1160
1161 #if ((BOARD == 43) || (BOARD == 45))
1162 // if Esample,Evaconso active extended page mode
1163 // With Calypso+ chipset, extended page mode can be enabled
1164 // only if W_A_CALYPSO_PLUS_SPR_19599 is set to one in l1_confg.h.
1165 // see L1_MCU-SPR-17515 and L1_MCU-SPR-19599 for more information
1166 f_memif_extended_page_mode_enable();
1167 #endif
1168 #endif /* (CHIPSET == 12) */
1169
1170 #if (CHIPSET == 15)
1171 /* API-RHEA control register configuration */
1172 f_emif_api_rhea_conf(C_RHEA_STROBE0_ACCESS_SIZE_ADAPT_ENABLE,
1173 C_RHEA_STROBE1_ACCESS_SIZE_ADAPT_ENABLE,
1174 C_API_ACCESS_SIZE_ADAPT_ENABLE,
1175 C_ARM_DEBUG_DISABLE);
1176 #if (BOARD == 70) || (BOARD == 71)
1177 // set the EMIF settings here for locosto
1178 // We could have the default settings here and
1179 // then change it after dynamic clock config
1180 /* MCP RAM Setting Is being done here */
1181 #if 0 /* This is commented out by Ranga */
1182 #if (PSP_FAILSAFE!=1)
1183 bcrTmpVal = *((volatile unsigned char *)0x007FFFFFE);
1184 bcrTmpVal +=1;
1185 bcrTmpVal = *((volatile unsigned char *)0x007FFFFFE);
1186 *((volatile unsigned char *)0x007FFFFFE)=0x0001;
1187 *((volatile unsigned char *)0x007FFFFFE)=0x1542;
1188
1189 /* Setting NOR Flash to these 3 Wait State */
1190 *((volatile char *)0x06000AAA)=0xAA;
1191 *((volatile char *)0x06000555)=0x55;
1192 *((volatile char *)0x06016AAA)=0xC0;
1193 #endif
1194 #endif
1195 #endif
1196 #endif /* (CHIPSET == 15) */
1197
1198
1199 /*
1200 * Initialize current DSP clock to 0 in order to pass through
1201 * the right DSP latency configuration (increase DSP clock)
1202 * in f_dynamic_clock_cfg().
1203 * Obviously, the real DSP clock is not 0kHz.
1204 * d_dsp_cur_clk will be updated after clock configuration in f_dynamic_clock_cfg().
1205 */
1206 d_dsp_cur_clk = 0; // Used to keep track of current DSP clock.
1207
1208 /* Dynamic clock configuration */
1209 f_dynamic_clock_cfg(C_CLOCK_CFG_DEFAULT);
1210
1211 // Write_en_0 = 0 , Write_en_1 = 0
1212 RHEA_INITARM(0,0);
1213
1214 #if (CHIPSET ==15)
1215 // Mark USB on 52 MHZ Clock
1216 *((volatile unsigned short *) (CLKM_CNTL_CLK_USB)) = 0x02;
1217 #endif
1218
1219 #if (CHIPSET == 12) || ((CHIPSET == 10) && (OP_WCP == 1))
1220 /* Allocate the 0.5 Mbits Shared RAM to the DSP */
1221 f_memif_shared_sram_allocation(C_MEMIF_DSPMS_0_5MBITS_TO_DSP);
1222 #endif
1223
1224 // INTH
1225 //--------------------------------------------------
1226 #if (CHIPSET == 12) || (CHIPSET == 15)
1227 #if (GSM_IDLE_RAM != 0)
1228 f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram); // setup configuration IT handlers
1229 #else
1230 f_inth_setup((T_INTH_CONFIG *)a_inth_config); // setup configuration IT handlers
1231 #endif
1232 #else
1233 IQ_SetupInterrupts();
1234 #endif
1235
1236
1237 #if (CHIPSET == 12) || (CHIPSET == 15)
1238 #if (OP_L1_STANDALONE == 0)
1239
1240 f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter);
1241 #endif
1242 f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP);
1243 #if (OP_L1_STANDALONE == 1)
1244 f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter);
1245 f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP);
1246 #endif
1247
1248 #else
1249 // DMA
1250 //--------------------------------------------------
1251 // channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same
1252 #if (OP_L1_STANDALONE == 0)
1253 DMA_ALLOCDMA(1,0,1,1); // Channel 1 used by DSP with RIF RX
1254 #endif
1255 #endif
1256
1257 /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
1258
1259 #else
1260
1261 // RHEA Bridge
1262 //--------------------------------------------------
1263 // ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F
1264 RHEA_INITRHEA(0,0,0x7F);
1265
1266 #if (CHIPSET == 6)
1267 // WS_H = 1 , WS_L = 15
1268 RHEA_INITAPI(1,15); // should be 0x01E1 for 65 Mhz
1269 #else
1270 // WS_H = 0 , WS_L = 7
1271 RHEA_INITAPI(0,7); // should be 0x0101 for 65 Mhz
1272 #endif
1273
1274 // Write_en_0 = 0 , Write_en_1 = 0
1275 RHEA_INITARM(0,0);
1276
1277 // INTH
1278 //--------------------------------------------------
1279 INTH_DISABLEALLIT; // MASK all it
1280 INTH_CLEAR; // reset IRQ/FIQ source
1281 IQ_SetupInterrupts();
1282
1283 // DMA
1284 //--------------------------------------------------
1285 // channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same
1286 DMA_ALLOCDMA(1,0,1,1); // should be 0x25 (channel 1 = lead)
1287
1288 #if (CHIPSET == 6)
1289 // Memory WS configuration for ULYSS/G1 (26 Mhz) board
1290 //-----------------------------------------------------
1291 MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0);
1292 #endif
1293
1294 // CLKM
1295 //--------------------------------------------------
1296 CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */
1297
1298 #if (CHIPSET == 6)
1299 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS | CLKM_VTCXO_26);
1300 #else
1301 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS);
1302 #endif
1303
1304 #endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
1305
1306 // Freeze ULPD timer ....
1307 //--------------------------------------------------
1308 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_INIT_REG ) = 0;
1309 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE;
1310
1311 // reset INC_SIXTEEN and INC_FRAC
1312 //--------------------------------------------------
1313 #if (OP_L1_STANDALONE == 1)
1314 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE);
1315 #else
1316 ULDP_INCSIXTEEN_UPDATE(132); //32768.29038 =>132, 32500 => 133
1317 // 26000 --> 166
1318 ULDP_INCFRAC_UPDATE(15840); //32768.29038 =>15840, 32500 => 21845
1319 // 26000 --> 43691
1320 #endif /* OP_L1_STANDALONE */
1321
1322 // program ULPD WAKE-UP ....
1323 //=================================================
1324 #if (CHIPSET == 2)
1325 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 2 frame
1326 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 31 periods
1327 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
1328 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
1329 #else
1330 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames
1331 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods
1332 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
1333 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
1334 *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods
1335 #endif
1336
1337 #if (CHIPSET == 15)
1338 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SLEEPN) = SETUP_SLEEPZ; // 0
1339 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SYSCLKEN) = SETUP_SYSCLKEN; // 255 clocks of 32 KHz for 7.8 ms DCXO delay for Locosto
1340 *((volatile SYS_UWORD16 *)0xFFFEF192) = 0x1; //CLRZ
1341 *((volatile SYS_UWORD16 *)0xFFFEF190) = 0x2; //SLPZ
1342 *((volatile SYS_UWORD16 *)0xFFFEF18E)= 0x2; //SYSCLKEN
1343 *((volatile SYS_UWORD16 *)0xFFFEF186) = 0x2; //CLK13_EN
1344 *((volatile SYS_UWORD16 *)0xFFFEF18A) = 0x2; //DRP_DBB_SYSCLK
1345
1346
1347
1348
1349 #endif
1350
1351 // Set Gauging versus HF (PLL)
1352 //=================================================
1353 ULDP_GAUGING_SET_HF; // Enable gauging versus HF
1354 ULDP_GAUGING_HF_PLL; // Gauging versus PLL
1355
1356 // current supply for quartz oscillation
1357 //=================================================
1358 #if (OP_L1_STANDALONE == 1)
1359 #if ((CHIPSET != 9) && (CHIPSET != 12) && (CHIPSET !=15)) // programming model changed for Ulysse C035, stay with default value
1360 *(volatile SYS_UWORD16 *)QUARTZ_REG = 0x27;
1361 #endif
1362 #else
1363 #if ((BOARD == 6) || (BOARD == 8) || (BOARD == 9) || (BOARD == 35) || (BOARD == 40) || (BOARD == 41))
1364 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x27;
1365 #elif (BOARD == 7)
1366 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x24;
1367 #endif
1368 #endif /* OP_L1_STANDALONE */
1369
1370 // stop Gauging if any (debug purpose ...)
1371 //--------------------------------------------------
1372 if ( *((volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG) & ULDP_GAUGING_EN)
1373 {
1374 volatile UWORD32 j;
1375 ULDP_GAUGING_STOP; /* Stop the gauging */
1376 /* wait for gauging it*/
1377 // one 32khz period = 401 periods of 13Mhz
1378 for (j=1; j<50; j++);
1379 while (! (* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING);
1380 }
1381
1382 #if (OP_L1_STANDALONE == 0)
1383 AI_ClockEnable ();
1384
1385 #if (BOARD == 7)
1386 // IOs configuration of the B-Sample in order to optimize the power consumption
1387 AI_InitIOConfig();
1388
1389 // Set LPG instead of DSR_MODEM
1390 *((volatile SYS_UWORD16 *) ASIC_CONF) |= 0x40;
1391 // Reset the PERM_ON bit of LCR_REG
1392 *((volatile SYS_UWORD16 *) MEM_LPG) &= ~(0x80);
1393 #elif ((BOARD == 8) || (BOARD == 9))
1394 // IOs configuration of the C-Sample in order to optimize the power consumption
1395 AI_InitIOConfig();
1396
1397 // set the debug latch to 0x00.
1398 *((volatile SYS_UWORD8 *) 0x2800000) = 0x00;
1399 #elif ((BOARD == 35) || (BOARD == 46))
1400 AI_InitIOConfig();
1401 // CSMI INTERFACE
1402 // Initialize CSMI clients for GSM control
1403 // and Fax/Data services
1404 CSMI_Init();
1405 GC_Initialize(); // GSM control initialization
1406 CU_Initialize(); // Trace initialization
1407 CF_Initialize(); // Fax/Data pre-initialization
1408 #elif ((BOARD == 40) || (BOARD == 41))
1409 // IOs configuration of the D-Sample in order to optimize the power consumption
1410 AI_InitIOConfig();
1411
1412 #ifdef BTEMOBILE
1413 // Reset BT chip by toggling the Island's nRESET_OUT signal
1414 *((volatile SYS_UWORD16 *) 0xFFFFFD04) |= 0x04;
1415 *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4);
1416 #endif
1417
1418 // set the debug latch to 0x0000.
1419 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
1420 #elif ((BOARD == 70) || (BOARD == 71))
1421 AI_InitIOConfig();
1422 /* Mark The System configuration According to I-Sample */
1423 /* Adding GPIO Mux Setting Here */
1424 pin_configuration_all(); // Init Tuned for Power Management
1425 /* A22 is Enabled in int.s hence not Here */
1426 /* FIXME: PULL_UP Enable and PULL UP Values Need to revisited */
1427
1428 /* Add code to find out the manufacture id of NOR flash*/
1429
1430 // Copy ffsdrv_device_id_read() function code to RAM. The only known
1431 // way to determine the size of the code is to look either in the
1432 // linker-generated map file or in the assember output file.
1433 ffsdrv_copy_code_to_ram((UWORD16 *) detect_code,
1434 (UWORD16 *) &ffsdrv_device_id_read,
1435 sizeof(detect_code));
1436
1437 // Combine bit 0 of the thumb mode function pointer with the address
1438 // of the code in RAM. Then call the detect function in RAM.
1439 myfp = (pf_t) (((int) &ffsdrv_device_id_read & 1) | (int) detect_code);
1440 (*myfp)(0x06000000, &manufact, device_id);
1441
1442 enable_ps_ram_burst();
1443
1444 if( 0x7e == device_id[0] )
1445 {
1446 enable_flash_burst();
1447 flash_device_id = 0x7E;
1448 }
1449 else
1450 {
1451 enable_flash_burst_mirror();
1452 flash_device_id = 0;
1453 }
1454
1455
1456 asm(" NOP");
1457 asm(" NOP");
1458 asm(" NOP");
1459 asm(" NOP");
1460 asm(" NOP");
1461 asm(" NOP");
1462 asm(" NOP");
1463 asm(" NOP");
1464
1465 #if 0 // Init Changed for tuning to Power Management -Old Init Commented
1466 /* Ball N9 Mapped to TSPACT_8 (TPU) */
1467 F_IO_CONFIG(C_CONF_GPIO_5,C_CONF_PUPD_EN|0x01);
1468 /* Ball A6 ND_WE */
1469 F_IO_CONFIG(C_CONF_GPIO_18,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1470 /* Ball C2 ND_RDY */
1471 F_IO_CONFIG(C_CONF_GPIO_34,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1472 /* Ball C3 ND_RE */
1473 F_IO_CONFIG(C_CONF_GPIO_31,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1474 /* BALL E5 CAM_D_4 */
1475 F_IO_CONFIG(C_CONF_ND_NWP,0x02);
1476 /* BALL F6 ND_CLE */
1477 F_IO_CONFIG(C_CONF_GPIO_32,C_CONF_PUPD_EN|0x01);
1478 /* BALL H8 ND_ALE */
1479 F_IO_CONFIG(C_CONF_GPIO_33,C_CONF_PUPD_EN|0x01);
1480 /* BALL E10 LCD_NCS0 */
1481 F_IO_CONFIG(C_CONF_GPIO_13,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1482 /* BALL C11 GPIO_10 */
1483 F_IO_CONFIG(C_CONF_GPIO_10,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1484 /* BALL D10 GPIO_11 */
1485 F_IO_CONFIG(C_CONF_GPIO_11,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1486 /* BALL M6 CAM_D_1 */
1487 F_IO_CONFIG(C_CONF_GPIO_0,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x02);
1488 /* BALL N5 CAM_D_0 */
1489 F_IO_CONFIG(C_CONF_GPIO_47,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x02);
1490 /* BALL A5 CAM_LCLK */
1491 F_IO_CONFIG(C_CONF_GPIO_21,0x01);
1492 /* BALL C6 CAM_XCLK */
1493 F_IO_CONFIG(C_CONF_GPIO_22,0x01);
1494 /* BALL E7 CAM_VS */
1495 F_IO_CONFIG(C_CONF_GPIO_20,0x01);
1496 /* BALL F8 CAM_HS */
1497 F_IO_CONFIG(C_CONF_GPIO_19,0x01);
1498 /* BALL K7 MCSI_TX */
1499 F_IO_CONFIG(C_CONF_GPIO_45,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1500 /* BALL M5 MCSI_FS */
1501 F_IO_CONFIG(C_CONF_GPIO_44,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1502 /* BALL N3 MCSI_CK */
1503 F_IO_CONFIG(C_CONF_GPIO_43,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1504 /* BALL P2 MCSI_RX */
1505 F_IO_CONFIG(C_CONF_GPIO_46,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1506 /* BALL B11 TSPACT_10 */
1507 F_IO_CONFIG(C_CONF_GPIO_12,C_CONF_PUPD_EN|0x01);
1508 /* BALL B3 CAM_D_5 */
1509 F_IO_CONFIG(C_CONF_GPIO_30,C_CONF_PUPD_EN|0x03);
1510 /* BALL C4 CAM_D_7 */
1511 F_IO_CONFIG(C_CONF_GPIO_28,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x03);
1512 /* BALL C5 SPI_DATA_MOSI */
1513 F_IO_CONFIG(C_CONF_GPIO_25,C_CONF_PUPD_EN|0x01);
1514 /* BALL E6 SPI_NCS0 */
1515 F_IO_CONFIG(C_CONF_GPIO_26,C_CONF_PUPD_EN|0x01);
1516 /* BALL F7 SPI_DATA_MIS0 */
1517 F_IO_CONFIG(C_CONF_GPIO_24,C_CONF_PUPD_EN|0x03);
1518 /* BALL G6 CAM_D_2 */
1519 F_IO_CONFIG(C_CONF_GPIO_7,C_CONF_PUPD_EN|0x05);
1520 /* BALL G7 CAM_D_6 */
1521 F_IO_CONFIG(C_CONF_GPIO_29,C_CONF_PUPD_EN|0x03);
1522 /* BALL G8 SPI_NCS1 */
1523 F_IO_CONFIG(C_CONF_GPIO_27,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1524 /* BALL G9 SPI_CLK */
1525 F_IO_CONFIG(C_CONF_GPIO_23,C_CONF_PUPD_EN|0x01);
1526 /* BALL L6 CKM */
1527 F_IO_CONFIG(C_CONF_GPIO_42,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
1528
1529 /*By default the muxed bus is given to LCD*/
1530 C_CONF_LCD_CAM_NAN_REG=0x03;
1531
1532 #endif // for #if 0 Init Changed for Power Management
1533 #endif // BOARD
1534
1535 // Enable HW Timers 1 & 2
1536 TM_EnableTimer (1);
1537 TM_EnableTimer (2);
1538
1539 asm(" NOP");
1540 asm(" NOP");
1541 asm(" NOP");
1542 asm(" NOP");
1543 asm(" NOP");
1544 asm(" NOP");
1545 asm(" NOP");
1546 asm(" NOP");
1547 asm(" NOP");
1548 asm(" NOP");
1549 asm(" NOP");
1550 asm(" NOP");
1551 asm(" NOP");
1552 asm(" NOP");
1553 asm(" NOP");
1554 asm(" NOP");
1555 asm(" NOP");
1556 asm(" NOP");
1557 asm(" NOP");
1558 asm(" NOP");
1559 asm(" NOP");
1560 asm(" NOP");
1561 asm(" NOP");
1562 asm(" NOP");
1563 #endif /* (OP_L1_STANDALONE == 0) */
1564
1565 #endif /* #if (BOARD == 5) */
1566 #if(OP_L1_STANDALONE == 1 && MIRROR_BIT == 1 ) //temp FIX for L1 standalone-this fix will work only for I-sample mirror bit
1567 //#if(OP_L1_STANDALONE == 1 )
1568 //AI_InitIOConfig();
1569 //pin_configuration_all(); // Init Tuned for Power Management
1570 //enable_ps_ram_burst();
1571 //enable_flash_burst_mirror();
1572 flash_device_id = 0;
1573 //asm(" NOP");
1574 //asm(" NOP");
1575 //asm(" NOP");
1576 //asm(" NOP");
1577 //asm(" NOP");
1578 //asm(" NOP");
1579 //asm(" NOP");
1580 //asm(" NOP");
1581 #elif(OP_L1_STANDALONE == 1 && MIRROR_BIT == 0 )
1582 flash_device_id = 0x7E;
1583 #endif
1584
1585
1586 #if GSM_IDLE_RAM_DEBUG
1587 #if (CHIPSET!=15)
1588 *((volatile SYS_UWORD16 *) 0xFFFE4806) = (0x0020);
1589 AI_ConfigBitAsOutput(3);
1590 AI_ConfigBitAsOutput(2);
1591 #endif
1592 #endif
1593 #if (CHIPSET==15)
1594 {
1595 volatile unsigned int * configReg=(volatile unsigned int *)0xFFFEF01C;
1596 *configReg &= 0xF7FF;
1597 }
1598 #endif
1599
1600 }
1601
1602 //--> Init Added for Power Management
1603 /*******************************************************
1604 Configure ALL I/O pins
1605 *******************************************************/
1606 void pin_configuration_all(void)
1607 {
1608 pin_configuration_bluetooth();
1609 pin_configuration_emifs();
1610 pin_configuration_system();
1611 pin_configuration_lcd_nand(0);
1612 pin_configuration_keypad();
1613 pin_configuration_sim();
1614 pin_configuration_radio();
1615 pin_configuration_usb();
1616 pin_configuration_camera_irda(1);
1617 }
1618
1619 /*******************************************************
1620 Configure Bluetooth I/O pins
1621 *******************************************************/
1622 void pin_configuration_bluetooth(void)
1623 {
1624 GPIO_DIRECTION_OUT(37); GPIO_CLEAR_OUTPUT(37); // BT_nSHUTDOWN
1625 CONF_GPIO_43 = MUX_CFG(1, PULLOFF); // MCSI_CK
1626 CONF_GPIO_44 = MUX_CFG(1, PULLOFF); // MCSI_FS
1627 CONF_GPIO_45 = MUX_CFG(1, PULLOFF); // MCSI_TX
1628 CONF_GPIO_46 = MUX_CFG(1, PULLOFF); // MCSI_RX
1629 CONF_UART_CTS = MUX_CFG(0, PULLOFF); // CTS
1630 CONF_UART_RX = MUX_CFG(0, PULLOFF); // RX
1631 CONF_UART_TX = MUX_CFG(0, PULLOFF); // TX
1632 CONF_GPIO_37 = MUX_CFG(0, PULLOFF); // BT_SHUTDOWN
1633 }
1634
1635 /*******************************************************
1636 Configure EMIFS I/O pins
1637 *******************************************************/
1638 void pin_configuration_emifs(void)
1639 {
1640 CONF_ADD_21 = MUX_CFG(0, PULLOFF); // ADD21
1641 CONF_GPIO_39 = MUX_CFG(1, PULLOFF); // ADD22
1642 CONF_GPIO_38 = MUX_CFG(0, PULLOFF); // nCS0
1643 CONF_NCS3 = MUX_CFG(0, PULLOFF); // nCS3
1644 CONF_ADV = MUX_CFG(0, PULLOFF); // ADV
1645 CONF_NMOE = MUX_CFG(0, PULLOFF); // nMOE
1646 CONF_RNW = MUX_CFG(0, PULLOFF); // RnW
1647 CONF_GPIO_42 = MUX_CFG(1, PULLOFF); // CKM
1648 CONF_NRDY = MUX_CFG(0, PULLUP); // nRDYMEM
1649 }
1650
1651 /*******************************************************
1652 Configure system I/O pins
1653 *******************************************************/
1654 void pin_configuration_system(void)
1655 {
1656 GPIO_DIRECTION_IN(1); // GPIO_1
1657 GPIO_DIRECTION_OUT(2); GPIO_CLEAR_OUTPUT(2); // SYS_RESET
1658 GPIO_DIRECTION_IN(10); // Not used (nEMU0)
1659 CONF_CK13MHZ_EN = MUX_CFG(0, PULLOFF); // CK13MHZ_EN
1660 CONF_ABB_IRQ = MUX_CFG(0, PULLUP); // ABB_IRQ
1661 CONF_GPIO_5 = MUX_CFG(1, PULLOFF); // STARTADC
1662 CONF_CDO = MUX_CFG(0, PULLOFF); // CDO (I2S)
1663 CONF_CSCLK = MUX_CFG(0, PULLOFF); // CSCLK (I2S)
1664 CONF_CSYNC = MUX_CFG(0, PULLOFF); // CSYNC (I2S)
1665 CONF_NBSCAN = MUX_CFG(0, PULLUP); // nBSCAN
1666 CONF_SPARE_3 = MUX_CFG(0, PULLUP); // Spare3
1667 CONF_TDO = MUX_CFG(0, PULLOFF); // TDO
1668
1669 // JTAG pulls are disabled on I-Sample due to external buffers.
1670 // CONF_TCK = MUX_CFG(0, PULLDOWN); // TCK
1671 // CONF_TDI = MUX_CFG(0, PULLUP); // TDI
1672 // CONF_TMS = MUX_CFG(0, PULLUP); // TMS
1673 // CONF_TRST = MUX_CFG(0, PULLUP); // TRST
1674 CONF_TCK = MUX_CFG(0, PULLOFF); // TCK
1675 CONF_TDI = MUX_CFG(0, PULLOFF); // TDI
1676 CONF_TMS = MUX_CFG(0, PULLOFF); // TMS
1677 CONF_TRST = MUX_CFG(0, PULLOFF); // TRST
1678
1679 CONF_VDR = MUX_CFG(0, PULLOFF); // VDR
1680 CONF_VFSRX = MUX_CFG(0, PULLDOWN); // VFSRX
1681 CONF_GPIO_1 = MUX_CFG(0, PULLUP); // Not used GPIO
1682 CONF_GPIO_2 = MUX_CFG(0, PULLOFF); // SYS_RESET
1683 CONF_GPIO_10 = MUX_CFG(1, PULLUP); // Not used (NEMU0)
1684 CONF_GPIO_12 = MUX_CFG(2, PULLOFF); // TSPACT10
1685 }
1686
1687 /*******************************************************
1688 Configure LCD and NAND Flash I/O pins
1689 Mode = 0 : LCD functional. NAND not functional
1690 Mode = 1 : NAND functional. LCD not functional
1691 *******************************************************/
1692 void pin_configuration_lcd_nand(int mode)
1693 {
1694 CONF_ND_CE1 = MUX_CFG(0, PULLOFF);
1695 CONF_GPIO_18 = MUX_CFG(1, PULLOFF); // ND_WE
1696 CONF_GPIO_31 = MUX_CFG(1, PULLOFF); // ND_RE
1697 CONF_GPIO_32 = MUX_CFG(1, PULLOFF); // ND_CLE
1698 CONF_GPIO_33 = MUX_CFG(1, PULLOFF); // ND_ALE
1699 CONF_GPIO_34 = MUX_CFG(1, PULLUP); // ND_RDY
1700 CONF_LCD_NRST = MUX_CFG(0, PULLOFF);
1701 CONF_LCD_RNW = MUX_CFG(0, PULLOFF);
1702 CONF_LCD_RS = MUX_CFG(0, PULLOFF);
1703 CONF_LCD_STB = MUX_CFG(0, PULLOFF);
1704 CONF_GPIO_13 = MUX_CFG(1, PULLOFF); // LCD_NCS0
1705 switch(mode)
1706 {
1707 case 0: // LCD
1708 CONF_LCD_DATA_0 = MUX_CFG(0, PULLOFF);
1709 CONF_LCD_DATA_1 = MUX_CFG(0, PULLOFF);
1710 CONF_LCD_DATA_2 = MUX_CFG(0, PULLOFF);
1711 CONF_LCD_DATA_3 = MUX_CFG(0, PULLOFF);
1712 CONF_LCD_DATA_4 = MUX_CFG(0, PULLOFF);
1713 CONF_LCD_DATA_5 = MUX_CFG(0, PULLOFF);
1714 CONF_LCD_DATA_6 = MUX_CFG(0, PULLOFF);
1715 CONF_LCD_DATA_7 = MUX_CFG(0, PULLOFF);
1716 break;
1717 case 1: // NAND
1718 CONF_LCD_DATA_0 = MUX_CFG(3, PULLOFF);
1719 CONF_LCD_DATA_1 = MUX_CFG(3, PULLOFF);
1720 CONF_LCD_DATA_2 = MUX_CFG(3, PULLOFF);
1721 CONF_LCD_DATA_3 = MUX_CFG(3, PULLOFF);
1722 CONF_LCD_DATA_4 = MUX_CFG(3, PULLOFF);
1723 CONF_LCD_DATA_5 = MUX_CFG(3, PULLOFF);
1724 CONF_LCD_DATA_6 = MUX_CFG(3, PULLOFF);
1725 CONF_LCD_DATA_7 = MUX_CFG(3, PULLOFF);
1726 break;
1727 }
1728 }
1729
1730 /*******************************************************
1731 Configure keypad pins
1732 *******************************************************/
1733 void pin_configuration_keypad(void)
1734 {
1735 CONF_GPIO_8 = MUX_CFG(0, PULLUP); // KBR4
1736 CONF_GPIO_9 = MUX_CFG(0, PULLOFF); // KBC4
1737 CONF_KBC_0 = MUX_CFG(0, PULLOFF);
1738 CONF_KBC_1 = MUX_CFG(0, PULLOFF);
1739 CONF_KBC_2 = MUX_CFG(0, PULLOFF);
1740 CONF_KBC_3 = MUX_CFG(0, PULLOFF);
1741 CONF_KBR_0 = MUX_CFG(0, PULLUP);
1742 CONF_KBR_1 = MUX_CFG(0, PULLUP);
1743 CONF_KBR_2 = MUX_CFG(0, PULLUP);
1744 CONF_KBR_3 = MUX_CFG(0, PULLUP);
1745 }
1746
1747 /*******************************************************
1748 Configure SIM I/O pins
1749 *******************************************************/
1750 void pin_configuration_sim(void)
1751 {
1752 CONF_SIM_CLK = MUX_CFG(0, PULLOFF);
1753 CONF_SIM_IO = MUX_CFG(0, PULLOFF);
1754 CONF_SIM_PWCTRL = MUX_CFG(0, PULLOFF);
1755 CONF_SIM_RST = MUX_CFG(0, PULLOFF);
1756 }
1757
1758 /*******************************************************
1759 Configure radio I/O pins
1760 *******************************************************/
1761 void pin_configuration_radio(void)
1762 {
1763 CONF_TSPACT_11 = MUX_CFG(0, PULLOFF);
1764 CONF_TSPACT_12 = MUX_CFG(0, PULLOFF);
1765 CONF_TSPACT_13 = MUX_CFG(0, PULLOFF);
1766 CONF_TSPACT_14 = MUX_CFG(0, PULLOFF);
1767 CONF_TSPACT_15 = MUX_CFG(0, PULLOFF);
1768 }
1769
1770 /*******************************************************
1771 Configure USB I/O pins
1772 *******************************************************/
1773 void pin_configuration_usb(void)
1774 {
1775 CONF_USB_BOOT = MUX_CFG(0, PULLOFF);
1776 CONF_USB_DAT = MUX_CFG(0, PULLDOWN);
1777 CONF_USB_RCV = MUX_CFG(0, PULLDOWN);
1778 //CONF_USB_SE0 = MUX_CFG(0, PULLUP); // to reduce 130 uA
1779 CONF_USB_SE0 = MUX_CFG(0, PULLOFF); // to reduce 130 uA
1780 CONF_USB_TXEN = MUX_CFG(0, PULLOFF);
1781 }
1782
1783 /*******************************************************
1784 Configure Camera and IrDA I/O pins
1785 Mode = 0 : IrDA functional. Camera not functional
1786 Mode = 1 : Camera functional. IrDA not functional
1787 Use mode 1 ONLY when camera is active i.e. use
1788 mode 0 during sleep
1789 *******************************************************/
1790 void pin_configuration_camera_irda(int mode)
1791 {
1792 GPIO_DIRECTION_OUT(17); GPIO_SET_OUTPUT(17); // CAM_PWDN
1793 GPIO_DIRECTION_OUT(11); GPIO_SET_OUTPUT(11); // Golden eye sleep
1794 GPIO_DIRECTION_OUT(35); GPIO_CLEAR_OUTPUT(35); // LED_TRCH
1795 GPIO_DIRECTION_OUT(4); GPIO_SET_OUTPUT(4); // nCAM_RST
1796 GPIO_DIRECTION_OUT(20); GPIO_CLEAR_OUTPUT(20); // CAM_D_3
1797 GPIO_DIRECTION_OUT(19); GPIO_CLEAR_OUTPUT(19); // CAM_HS
1798 GPIO_DIRECTION_OUT(21); GPIO_CLEAR_OUTPUT(21); // CAM_LCLK
1799 GPIO_DIRECTION_OUT(36); GPIO_SET_OUTPUT(36); // IrDA_SD
1800 CONF_GPIO_36 = MUX_CFG(0, PULLOFF); // IRDA_SD
1801 CONF_GPIO_11 = MUX_CFG(1, PULLOFF); // Golden eye sleep (NEMU1)
1802 CONF_GPIO_4 = MUX_CFG(0, PULLOFF); // CAM_RESET
1803 CONF_GPIO_35 = MUX_CFG(0, PULLOFF); // LED_TORCH
1804 CONF_GPIO_17 = MUX_CFG(0, PULLOFF); // CAM_PWDN
1805 CONF_GPIO_23 = MUX_CFG(1, PULLDOWN); // SPI_CLK
1806 CONF_GPIO_24 = MUX_CFG(1, PULLDOWN); // SPI_DATA_MISO
1807 CONF_GPIO_25 = MUX_CFG(1, PULLDOWN); // SPI_DATA_MOSI
1808 CONF_GPIO_26 = MUX_CFG(1, PULLUP); // SPI_NCS0
1809 CONF_GPIO_27 = MUX_CFG(1, PULLUP); // SPI_NCS1
1810 CONF_GPIO_22 = MUX_CFG(1, PULLOFF); // CAM_XCLK
1811 switch(mode)
1812 {
1813 case 0: // IrDA or sleep
1814 CONF_GPIO_47 = MUX_CFG(1, PULLUP); // IrDA RXIR
1815 CONF_GPIO_0 = MUX_CFG(1, PULLOFF); // IrDA TXIR
1816 CONF_GPIO_7 = MUX_CFG(5, PULLDOWN); // CAM_D_2
1817 CONF_GPIO_20 = MUX_CFG(0, PULLOFF); // CAM_D_3 = GPIO
1818 CONF_ND_NWP = MUX_CFG(0, PULLOFF); // CAM_D_4 = ND_NWP
1819 CONF_GPIO_30 = MUX_CFG(3, PULLDOWN); // CAM_D_5
1820 CONF_GPIO_29 = MUX_CFG(3, PULLDOWN); // CAM_D_6
1821 CONF_GPIO_28 = MUX_CFG(3, PULLUP); // CAM_D_7
1822 CONF_GPIO_19 = MUX_CFG(0, PULLOFF); // CAM_HS = GPIO
1823 CONF_GPIO_21 = MUX_CFG(0, PULLOFF); // CAM_LCLK = GPIO
1824 break;
1825 case 1: // Camera
1826 CONF_GPIO_47 = MUX_CFG(2, PULLOFF); // CAM_D_0 + IrDA
1827 CONF_GPIO_0 = MUX_CFG(2, PULLOFF); // CAM_D_1 + IrDA
1828 CONF_GPIO_7 = MUX_CFG(5, PULLOFF); // CAM_D_2
1829 CONF_GPIO_20 = MUX_CFG(2, PULLOFF); // CAM_D_3
1830 CONF_ND_NWP = MUX_CFG(2, PULLOFF); // CAM_D_4
1831 CONF_GPIO_30 = MUX_CFG(3, PULLOFF); // CAM_D_5
1832 CONF_GPIO_29 = MUX_CFG(3, PULLOFF); // CAM_D_6
1833 CONF_GPIO_28 = MUX_CFG(3, PULLOFF); // CAM_D_7
1834 CONF_GPIO_19 = MUX_CFG(1, PULLOFF); // CAM_HS
1835 CONF_GPIO_21 = MUX_CFG(1, PULLOFF); // CAM_LCLK
1836 break;
1837 }
1838 }
1839
1840 //<-- Init Added for Power Management
1841
1842 /*
1843 * Init_Drivers
1844 *
1845 * Performs Drivers Initialization.
1846 */
1847 void Set_Switch_ON_Cause(void);
1848 void Init_Drivers(void)
1849 {
1850
1851 #if (CHIPSET==15)
1852 bspI2c_init();
1853 bspTwl3029_init();
1854
1855 #if (OP_L1_STANDALONE == 0)
1856 Set_Switch_ON_Cause();
1857 #endif
1858
1859
1860 /* Turn on DRP We will make VRMCC to device group Modem
1861 * And Switch it on.
1862 */
1863 bspTwl3029_Power_setDevGrp(NULL,BSP_TWL3029_POWER_VRMMC,BSP_TWL3029_POWER_DEV_GRP_MODEM);
1864 wait_ARM_cycles(convert_nanosec_to_cycles(100000*2));
1865 bspTwl3029_Power_enable(NULL,BSP_TWL3029_POWER_VRMMC,BSP_TWL3029_POWER_STATE_ACTIVE);
1866 #endif
1867
1868 #if (CHIPSET!=15)
1869 #if ABB_SEMAPHORE_PROTECTION
1870 // Create the ABB semaphore
1871 ABB_Sem_Create();
1872 #endif // SEMAPHORE_PROTECTION
1873 #endif
1874
1875 #if (OP_L1_STANDALONE == 0)
1876 /*
1877 * Initialize FFS invoking restore procedure by MPU-S
1878 */
1879 #if ((BOARD == 35) || (BOARD == 46))
1880 GC_FfsRestore();
1881 #endif
1882
1883 /*
1884 * FFS main initialization.
1885 */
1886
1887 ffs_main_init();
1888
1889
1890 /*
1891 * Initialize Riviera manager and create tasks thanks to it.
1892 */
1893 #if (CHIPSET!=15) || (REMU==0)
1894 rvf_init();
1895 rvm_init(); /* A-M-E-M-D-E-D! */
1896 create_tasks();
1897 #endif
1898 /*
1899 * SIM Main Initialization.
1900 */
1901 #if (CHIPSET!=15)
1902 SIM_Initialize ();
1903 #else
1904 bspUicc_bootInit();
1905 #endif
1906 #endif
1907 }
1908
1909 #if (PSP_STANDALONE == 0)
1910 /*
1911 * l1_create_HISR
1912 *
1913 * Create L1 HISR.
1914 */
1915 void l1_create_HISR (void)
1916 {
1917 STATUS status;
1918
1919 #if (OP_L1_STANDALONE == 0)
1920 // Fill the entire stack with the pattern 0xFE
1921 memset (layer_1_sync_stack, 0xFE, LAYER_1_SYNC_STACK_SIZE);
1922 #endif
1923
1924 status = NU_Create_HISR (&layer_1_sync_HISR,
1925 "L1_HISR",
1926 layer_1_sync_HISR_entry,
1927 #if (OP_L1_STANDALONE == 0)
1928 1,
1929 layer_1_sync_stack,
1930 LAYER_1_SYNC_STACK_SIZE);
1931 #else
1932 1,
1933 layer_1_sync_stack,
1934 sizeof(layer_1_sync_stack));
1935 #endif
1936
1937 #if (L1_EXT_AUDIO_MGT)
1938 // Create HISR for Ext MIDI activity
1939 //==================================
1940 status += NU_Create_HISR(&EXT_AUDIO_MGT_hisr,
1941 "H_EXT_AUDIO_MGT",
1942 Cust_ext_audio_mgt_hisr,
1943 2,
1944 ext_audio_mgt_hisr_stack,
1945 sizeof(ext_audio_mgt_hisr_stack));
1946 #endif
1947
1948 #if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) ) // equivalent to an API_HISR flag
1949 status += NU_Create_HISR(&apiHISR,
1950 "API_HISR",
1951 api_hisr,
1952 2,
1953 API_HISR_stack,
1954 sizeof(API_HISR_stack));
1955 #endif // (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1)
1956
1957 #if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1) // equivalent to an API_MODEM_HISR flag
1958 // Create HISR for USF DSP interrupt !!!!. This HISR needs
1959 // to have the highest priority since the USF status needs
1960 // to be known before the next block starts.
1961 //========================================================
1962 status += NU_Create_HISR(&api_modemHISR,
1963 "MODEM",
1964 api_modem_hisr,
1965 1,
1966 API_MODEM_HISR_stack,
1967 sizeof(API_MODEM_HISR_stack));
1968 #endif
1969
1970 assert (status == 0);
1971 }
1972
1973
1974 void l1_create_ISR (void)
1975 {
1976 l1_create_HISR();
1977 }
1978 #endif
1979
1980 #endif /* (CODE_VERSION != SIMULATION) */
1981
1982
1983
1984 /*
1985 * Init_Unmask_IT
1986 *
1987 * Unmask all used interrupts.
1988 */
1989
1990 void Init_Unmask_IT (void)
1991 {
1992 #if (CODE_VERSION != SIMULATION)
1993 /* Reset all current interrupts */
1994 #if (CHIPSET == 12) || (CHIPSET == 15)
1995 F_INTH2_VALID_NEXT(C_INTH_IRQ); /* Reset current IT in INTH2 IRQ */
1996 F_INTH_VALID_NEXT(C_INTH_IRQ); /* Reset current IT in INTH IRQ */
1997 F_INTH_VALID_NEXT(C_INTH_FIQ); /* Reset current IT in INTH FIQ */
1998 F_INTH_RESET_ALL_IT; /* Reset all IRQ/FIQ source */
1999 #elif ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
2000 INTH_RESETALLIT;
2001 INTH_CLEAR; /* reset IRQ/FIQ source */
2002 #endif
2003
2004 // Disable all the IRQs of ARM before unmasking the interrupts. And enable them once the unmasking is
2005 // complete. This will ensure that no context switch happens due to coming of an already unmasked interrupt
2006 // before completing the unmasking of the rest of the interrupts. If the context switch happens in
2007 // before all the interrupts have been unmasked, then the control will never return to this function
2008 //since it will go to TCT_Scheduler() and so some interrupts may remain masked.
2009 INT_DisableIRQ();
2010
2011 // SL: TEMPORARY FIX FOR BUG ON P2
2012 // FRAME INTERRUPT STAY MASKED
2013 #if ((BOARD == 35) || (BOARD == 46))
2014 INTH_ENABLEONEIT(IQ_FRAME);
2015 #endif
2016 // TEMPORARY FIX FOR BUG ON P2
2017
2018
2019 /* Enable Uart Modem and IrDA interrupts */
2020 #if ((((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || \
2021 (TESTMODE) || (TRACE_TYPE==7)) && (OP_L1_STANDALONE == 1)) || \
2022 (OP_L1_STANDALONE == 0))
2023
2024 #if (CHIPSET == 12) || (CHIPSET == 15)
2025 F_INTH_ENABLE_ONE_IT (C_INTH_UART_IRDA_IT); /* Enable UART_IRDA interrupts */
2026 #if (CHIPSET == 12)
2027 F_INTH_ENABLE_ONE_IT(C_INTH_UART_MODEM1_IT); /* Enable UART_MODEM interrupts */
2028 #endif
2029 #else
2030 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || \
2031 (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
2032 #if ((BOARD != 35) && (BOARD != 46))
2033 INTH_ENABLEONEIT (IQ_UART_IRDA_IT); /* Enable UART_IRDA interrupts */
2034 #endif
2035 #endif
2036 INTH_ENABLEONEIT (IQ_UART_IT); /* Enable UART_MODEM interrupts */
2037 #endif
2038
2039 #if (OP_L1_STANDALONE == 1)
2040 #if (CHIPSET == 12)
2041 F_INTH_ENABLE_ONE_IT (C_INTH_UART_MODEM2_IT); /* Enable UART_MODEM2 interrupts */
2042 #endif
2043 #endif /* (OP_L1_STANDALONE == 1) */
2044
2045 #endif /* (TRACE_TYPE ...) || (OP_L1_STANDALONE == 0) */
2046
2047 /* Enable other interrupts */
2048 #if (OP_L1_STANDALONE == 1)
2049 if (l1_config.pwr_mngt == PWR_MNGT)
2050 {
2051
2052 #if GEMINI_TIMER
2053 #if (CHIPSET == 12) || (CHIPSET == 15)
2054 F_INTH_ENABLE_ONE_IT(C_INTH_TIMER1_IT); /* Enable Timer1 interrupt */
2055 #else
2056 INTH_ENABLEONEIT(IQ_TIM1); /* Enable Timer1 interrupt */
2057 #endif
2058 #endif
2059
2060 #if EXT_IRQ
2061 #if (CHIPSET == 12) || (CHIPSET == 15)
2062 F_INTH_ENABLE_ONE_IT (C_INTH_ABB_IRQ_IT); /* Enable ABB_IRQ_IT EXT_IRQ */
2063 #else
2064 INTH_ENABLEONEIT(IQ_EXT); /* Enable External interrupt */
2065 #endif
2066 #endif
2067 }
2068
2069 #else
2070 #if ((CHIPSET == 12) || (CHIPSET == 15))
2071 F_INTH_ENABLE_ONE_IT(C_INTH_KEYBOARD_IT);
2072 #else
2073 #if ((BOARD == 35) || (BOARD == 46))
2074 INTH_ENABLEONEIT (IQ_ICR);
2075 #else
2076 INTH_ENABLEONEIT (IQ_ARMIO); /* Enable Keypad/GPIO Interrupt */
2077 #endif
2078 #endif /* (CHIPSET == 12) */
2079 #endif /* OP_L1_STANDALONE */
2080
2081
2082 #if (CHIPSET == 12) || (CHIPSET == 15)
2083 //enable LEAD2 interrupt
2084 F_INTH_ENABLE_ONE_IT (C_INTH_API_IT);
2085 #else
2086 //enable LEAD2 interrupt
2087 INTH_ENABLEONEIT(IQ_API);
2088 #endif
2089
2090
2091 /* Enable TDMA interrupt */
2092 #if ((CHIPSET == 12) || (CHIPSET == 15))
2093 #if (PSP_STANDALONE == 0)
2094 F_INTH_ENABLE_ONE_IT (C_INTH_FRAME_IT);
2095 #endif
2096 #else
2097 INTH_ENABLEONEIT(IQ_FRAME);
2098 #endif
2099 //--> to enable DMA Interrupt for Lite
2100 #if ((CHIPSET == 15) )
2101 #if (LOCOSTO_LITE == 1)
2102 F_INTH_ENABLE_ONE_IT (C_INTH_DMA_IT);
2103 #endif
2104 #endif
2105 //<-- to enable DMA Interrupt for Lite
2106
2107 #if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) )
2108 #if (CHIPSET == 12) || (CHIPSET == 15)
2109 F_INTH_ENABLE_ONE_IT(C_INTH_API_IT); // Enable API interrupt
2110 #elif (CHIPSET == 10)
2111 #if (L1_DYN_DSP_DWNLD == 1)
2112
2113 //enable interrupt
2114 INTH_ENABLEONEIT (IQ_API);
2115
2116 #endif // L1_DYN_DSP_DWNLD == 1
2117 #endif // CHIPSET
2118 #endif // (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC ==1) || (L1_DYN_DSP_DWNLD == 1)
2119 // Enable the ARM IRQs once all the interrupts have been unmasked.
2120 INT_EnableIRQ();
2121 #endif /* NO SIMULATION */
2122 }
2123
2124
2125 /*
2126 * Init_Serial_Flows
2127 *
2128 * Performs Serialswitch + related serial data flows initialization.
2129 */
2130
2131 void Init_Serial_Flows (void)
2132 {
2133 #if (OP_L1_STANDALONE == 0)
2134
2135 /*
2136 * Initialize Serial Switch module.
2137 */
2138 #if ((BOARD==35) || (BOARD == 46))
2139 SER_InitSerialConfig (GC_GetSerialConfig());
2140 #else
2141 SER_InitSerialConfig (&appli_ser_cfg_info);
2142 #endif
2143 /*
2144 * Then Initialize the Serial Data Flows and the associated UARTs:
2145 * - G2-3 Trace if GSM/GPRS Protocol Stack
2146 * - AT-Cmd/Fax & Data Flow
2147 *
2148 * Layer1/Riviera Trace Flow and Bluetooth HCI Flow are initialized
2149 * by the appropriate SW Entities.
2150 *
2151 * G2-3 Trace => No more Used
2152 */
2153 SER_tr_Init(SER_PROTOCOL_STACK, TR_BAUD_38400, NULL);
2154
2155 /*
2156 * Fax & Data / AT-Command Interpreter Serial Data Flow Initialization
2157 */
2158
2159 #if ((BOARD != 35) && (BOARD != 46))
2160 (void) SER_fd_Initialize ();
2161 #endif
2162 #else /* OP_L1_STANDALONE */
2163
2164 #if (TESTMODE || (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==6) || (TRACE_TYPE==7))
2165 #if ((BOARD == 35) || (BOARD == 46))
2166 ser_cfg_info[UA_UART_0] = '0';
2167 #else
2168 ser_cfg_info[UA_UART_0] = 'G';
2169 #endif
2170 #if (CHIPSET !=15)
2171 ser_cfg_info[UA_UART_1] = 'R'; // Riviear Demux on UART MODEM
2172 #else
2173 ser_cfg_info[UA_UART_0] = 'R'; // Riviear Demux on UART MODEM
2174 #endif
2175
2176 /* init Uart Modem */
2177 SER_InitSerialConfig (&appli_ser_cfg_info);
2178
2179 #if TESTMODE || (TRACE_TYPE == 1) || (TRACE_TYPE == 7)
2180 SER_tr_Init (SER_LAYER_1, TR_BAUD_115200, rvt_activate_RX_HISR);
2181
2182 rvt_register_id("OTHER",&trace_id,(RVT_CALLBACK_FUNC)NULL);
2183 #else
2184 SER_tr_Init (SER_LAYER_1, TR_BAUD_38400, NULL);
2185 #endif
2186
2187 L1_trace_string(" \n\r");
2188
2189 #endif /* TRACE_TYPE */
2190
2191 #endif /* OP_L1_STANDALONE */
2192 }
2193
2194 // From this point, everything is compiled to execute in internal RAM
2195
2196 #if (((MOVE_IN_INTERNAL_RAM == 1) ^ (GSM_IDLE_RAM != 0)) && (GSM_IDLE_RAM != 0))
2197 #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START
2198 #if (CODE_VERSION != SIMULATION)
2199
2200 #if ((CHIPSET == 12) || (CHIPSET==15))
2201
2202 #if GSM_IDLE_RAM_DEBUG
2203 void flash_access_handler(void)
2204 {
2205 l1s.gsm_idle_ram_ctl.killing_flash_access++;
2206 }
2207 void ext_ram_access_handler(void)
2208 {
2209 l1s.gsm_idle_ram_ctl.killing_ext_ram_access++;
2210 }
2211 #endif
2212
2213 void ext_ram_irq_inth_handler(void)
2214 {
2215 if (!READ_TRAFFIC_CONT_STATE)
2216 CSMI_TrafficControllerOn();
2217 a_inth_config[F_INTH_GET_IRQ].d_it_handler();
2218 }
2219
2220 void ext_ram_fiq_inth_handler(void)
2221 {
2222 if (!READ_TRAFFIC_CONT_STATE)
2223 CSMI_TrafficControllerOn();
2224 a_inth_config[F_INTH_GET_FIQ].d_it_handler();
2225 }
2226 #endif
2227 #endif // (CODE_VERSION != SIMULATION)
2228 #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
2229 #endif
2230
2231 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0))
2232 #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START
2233
2234 #if (PSP_STANDALONE == 0)
2235 /*-------------------------------------------------------*/
2236 /* TP_FrameIntHandler() Low Interrupt service routine */
2237 /*-------------------------------------------------------*/
2238 /* Parameters : */
2239 /* Return : */
2240 /* Functionality : activate Hisr on each frame interrupt*/
2241 /*-------------------------------------------------------*/
2242 void TP_FrameIntHandler(void)
2243 {
2244
2245 #if (OP_L1_STANDALONE == 1)
2246
2247 #if (TRACE_TYPE==1)
2248 if (trace_info.current_config->l1_dyn_trace & 1<<L1_DYN_TRACE_L1S_CPU_LOAD)
2249 {
2250 TM_ResetTimer (2, 0xFFFF, 1, 0);
2251 TM_StartTimer (2);
2252 }
2253 #endif
2254
2255 #if (TRACE_TYPE==6)
2256 TM_ResetTimer (2, 0xFFFF, 1, 0);
2257 TM_StartTimer (2);
2258 #endif
2259
2260 #if (TRACE_TYPE==7) /* CPU_LOAD */
2261 l1_cpu_load_start();
2262 #endif
2263
2264 #else
2265
2266 #if (TRACE_TYPE == 4) && (TI_NUC_MONITOR != 1)
2267 // TM_ResetTimer (2, TIMER_RESET_VALUE, 1, 0);
2268 // TM_StartTimer (2);
2269 #endif
2270
2271
2272 #if (TI_NUC_MONITOR == 1)
2273 /* Copy LISR buffer in Log buffer each end of HISR */
2274 ti_nuc_monitor_tdma_action();
2275 #endif
2276
2277 #if WCP_PROF == 1
2278 prf_LogFNSwitch(l1s.actual_time.fn_mod42432);
2279 #endif
2280
2281 #endif /* OP_L1_STANDALONE */
2282
2283 NU_Activate_HISR(&layer_1_sync_HISR); /* Activate HISR interrupt */
2284
2285 #if (OP_L1_STANDALONE == 0)
2286 #if (WCP_PROF == 1)
2287 #if (PRF_CALIBRATION == 1)
2288 NU_Activate_HISR(&prf_CalibrationHISR);
2289 #endif
2290 #endif
2291 #endif
2292
2293 }
2294 #endif
2295
2296 /*
2297 * layer_1_sync_HISR_entry
2298 *
2299 * HISR associated to layer 1 sync.
2300 */
2301
2302 void layer_1_sync_HISR_entry (void)
2303 {
2304 #if (PSP_STANDALONE==0)
2305 // Call Synchronous Layer1
2306 hisr();
2307 #endif
2308 }
2309 #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
2310 #endif // !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0))
2311
2312 #if (PSP_STANDALONE == 1)
2313
2314 #include "nucleus.h"
2315 #include "tc_defs.h"
2316
2317 extern TC_PROTECT TCD_System_Protect;
2318
2319 /*-------------------------------------------------------*/
2320 /* int OS_system_protect() */
2321 /*-------------------------------------------------------*/
2322 /* Parameters : none */
2323 /* Return : The Thread Control Block of the thread */
2324 /* which already owns the protection or */
2325 /* 0 if no protection */
2326 /* Functionality : Checks whether the system structures */
2327 /* are already protected or not */
2328 /*-------------------------------------------------------*/
2329 void OS_system_protect (void)
2330 {
2331 NU_Protect((NU_PROTECT*) &TCD_System_Protect);
2332 }
2333
2334 /*-------------------------------------------------------*/
2335 /* int OS_system_Unprotect() */
2336 /*-------------------------------------------------------*/
2337 /* Parameters : none */
2338 /* Return : */
2339 /* Functionality : unprotect the system structures */
2340 /*-------------------------------------------------------*/
2341 void OS_system_Unprotect (void)
2342 {
2343 NU_Unprotect();
2344 }
2345
2346 void bspDummy_detect(void* a,int b, void* c)
2347 {
2348 return;
2349 }
2350
2351 void bspDummy_remove(int a)
2352 {
2353 return;
2354 }
2355
2356 void Init_Watchdog_Timer(void)
2357 {
2358 /* This code is for PSP STANDALONE Build Only */
2359 /* WatchDog will be used by DAR enity, so using TIMER1 for OS Ticks
2360 This will give tick period roughly equle to 4.5 ms which approx
2361 Frame Interrupt timing */
2362 Dtimer1_Init_cntl(0XE9, 1, 0x07, 1);
2363 Dtimer1_Start(1);
2364 F_INTH_ENABLE_ONE_IT(C_INTH_TIMER1_IT);
2365 bspUicc_drvRegister((BspUicc_CardPresentDetectHandler)bspDummy_detect,
2366 (BspUicc_CardAbsentDetectHandler) bspDummy_remove);
2367 }
2368
2369 #endif