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comparison doc/FCDEV3B-hardware-bug @ 483:15c61c8f3166

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doc/FCDEV3B-hardware-bug: update on the investigation and the proposed fix
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 20 Jun 2018 07:53:32 +0000
parents 8fbf3c0ea8b6
children
comparison
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482:ad7f986afae3 483:15c61c8f3166
15 reset that happens as part of flash boot mode 1, the FDP output behaviour 15 reset that happens as part of flash boot mode 1, the FDP output behaviour
16 during that watchdog reset, and the flash chip's reaction to the latter. 16 during that watchdog reset, and the flash chip's reaction to the latter.
17 17
18 * On all of the boards there is a problem with sleep modes: when the firmware 18 * On all of the boards there is a problem with sleep modes: when the firmware
19 is running from flash as opposed to RAM, certain sleep-wake sequences cause 19 is running from flash as opposed to RAM, certain sleep-wake sequences cause
20 an erratic self-reboot or a hang. It is suspected (though not proven yet) 20 an erratic self-reboot or a hang. Oscilloscope probing on a decased Pirelli
21 that the FDP output goes low during all sleep modes, our Spansion flash chip 21 DP-L10 motherboard on which Calypso's FDP output is accessible seems to
22 gets unhappy with the reset timing it gets subjected to, and some flash reads 22 confirm my (Mychaela's) suspicion that this FDP signal goes low during all
23 (instruction fetches) don't work after wakeup. So far the only workable 23 sleep modes, and the current working hypothesis is that our Spansion flash
24 chip gets unhappy with the reset timing it gets subjected to, and some flash
25 reads (instruction fetches) don't work after wakeup. So far the only workable
24 solution has been to disable all sleep modes in all FCDEV3B fw builds; 26 solution has been to disable all sleep modes in all FCDEV3B fw builds;
25 nothing else has been successful. 27 nothing else has been successful. However, re-enabling all of these sleep
28 modes with AT%SLEEP=4 works fine when the firmware image executes out of RAM
29 instead of flash, further supporting our current working hypothesis as to the
30 root cause.
26 31
27 The fcdev3b-hacks directory contains two hacks that can be applied to FCDEV3B 32 The fcdev3b-hacks directory contains two hacks that can be applied to FCDEV3B
28 firmware images (fwimage.bin builds) as xxd binary patches: 33 firmware images (fwimage.bin builds) as xxd binary patches:
29 34
30 * The first hack dating from 2017-05 patches the fw to use flash boot mode 0 35 * The first hack dating from 2017-05 patches the fw to use flash boot mode 0
41 go away by having the Calypso execute some cycles out of its internal ROM and 46 go away by having the Calypso execute some cycles out of its internal ROM and
42 RAM before hitting the flash after wakeup, but nope, bringing up the SIM 47 RAM before hitting the flash after wakeup, but nope, bringing up the SIM
43 interface with AT+CFUN=1 in the l1reconst config when running from flash with 48 interface with AT+CFUN=1 in the l1reconst config when running from flash with
44 small sleep enabled still triggers erratic misbehaviour even with this patch. 49 small sleep enabled still triggers erratic misbehaviour even with this patch.
45 50
46 The proper fix will be to change the PCB to not connect the flash chip's reset 51 The proper fix will require a new PCB spin to change the flash reset wiring:
47 input to FDP any more, and connect it to a pull-up resistor instead. But this 52 instead of driving it with Calypso's FDP output, use the ON_nOFF master reset
48 fix will require an expensive PCB respin, hence some experiments to test this 53 signal from Iota's VRPC block, fed through a logic voltage level translating
49 idea will need to be done first. 54 buffer to change it from 1.5 V to 2.8 V logic. The flash chip we are using has
55 lower power consumption when it is NOT held in reset, hence unlike TI's intent
56 with FDP, we don't want our flash chip to go into reset during any sleep at all.
57
58 The new PCB revision with this change is now in the process of being finalized,
59 and we will soon need the funding to produce the new boards. Anyone who is
60 interested in helping to make FCDEV3B V2 a reality should email Mychaela.