FreeCalypso > hg > fc-magnetite

comparison src/cs/drivers/drv_app/ffs/board/drv.c @ 85:204d6866901b

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FFS changes to support C139, Pirelli and future FreeCalypso targets
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 02 Oct 2016 08:10:40 +0000
parents 945cf7f506b2
children 7aad22344e77
comparison
equal deleted inserted replaced
84:42d766231c46 85:204d6866901b
242 void ffsdrv_amd_write_end(void); 242 void ffsdrv_amd_write_end(void);
243 void ffsdrv_amd_erase_end(void); 243 void ffsdrv_amd_erase_end(void);
244 244
245 void ffsdrv_amd_write_halfword(volatile uint16 *addr, uint16 value) 245 void ffsdrv_amd_write_halfword(volatile uint16 *addr, uint16 value)
246 { 246 {
247 volatile char *flash = dev.base; 247 volatile uint16 *flash = (volatile uint16 *)dev.base;
248 uint32 cpsr; 248 uint32 cpsr;
249 249
250 tlw(led_on(LED_WRITE)); 250 tlw(led_on(LED_WRITE));
251 ttw(ttr(TTrDrvWrite, "wh(%x,%x)" NL, addr, value)); 251 ttw(ttr(TTrDrvWrite, "wh(%x,%x)" NL, addr, value));
252 252
259 } 259 }
260 260
261 cpsr = int_disable(); 261 cpsr = int_disable();
262 tlw(led_toggle(LED_WRITE_SUSPEND)); 262 tlw(led_toggle(LED_WRITE_SUSPEND));
263 dev.state = DEV_WRITE; 263 dev.state = DEV_WRITE;
264 flash[0xAAAA] = 0xAA; // unlock cycle 1 264 flash[0x555] = 0xAA; // unlock cycle 1
265 flash[0x5555] = 0x55; // unlock cycle 2 265 flash[0x2AA] = 0x55; // unlock cycle 2
266 flash[0xAAAA] = 0xA0; 266 flash[0x555] = 0xA0;
267 *addr = value; 267 *addr = value;
268 int_enable(cpsr); 268 int_enable(cpsr);
269 tlw(led_toggle(LED_WRITE_SUSPEND)); 269 tlw(led_toggle(LED_WRITE_SUSPEND));
270 270
271 ffsdrv_amd_write_end(); 271 ffsdrv_amd_write_end();
304 tlw(led_off(LED_WRITE)); 304 tlw(led_off(LED_WRITE));
305 } 305 }
306 306
307 void ffsdrv_amd_erase(uint8 block) 307 void ffsdrv_amd_erase(uint8 block)
308 { 308 {
309 volatile char *flash = dev.base; 309 volatile uint16 *flash = (volatile uint16 *)dev.base;
310 uint32 cpsr; 310 uint32 cpsr;
311 311
312 tlw(led_on(LED_ERASE)); 312 tlw(led_on(LED_ERASE));
313 ttw(ttr(TTrDrvErase, "e(%d)" NL, block)); 313 ttw(ttr(TTrDrvErase, "e(%d)" NL, block));
314 314
315 dev.addr = (uint16 *) block2addr(block); 315 dev.addr = (uint16 *) block2addr(block);
316 316
317 cpsr = int_disable(); 317 cpsr = int_disable();
318 dev.state = DEV_ERASE; 318 dev.state = DEV_ERASE;
319 flash[0xAAAA] = 0xAA; // unlock cycle 1 319 flash[0x555] = 0xAA; // unlock cycle 1
320 flash[0x5555] = 0x55; // unlock cycle 2 320 flash[0x2AA] = 0x55; // unlock cycle 2
321 flash[0xAAAA] = 0x80; 321 flash[0x555] = 0x80;
322 flash[0xAAAA] = 0xAA; // unlock cycle 1 322 flash[0x555] = 0xAA; // unlock cycle 1
323 flash[0x5555] = 0x55; // unlock cycle 2 323 flash[0x2AA] = 0x55; // unlock cycle 2
324 *dev.addr = 0x30; // AMD erase sector command 324 *dev.addr = 0x30; // AMD erase sector command
325 int_enable(cpsr); 325 int_enable(cpsr);
326 326
327 ffsdrv_amd_erase_end(); 327 ffsdrv_amd_erase_end();
328 } 328 }