--- a/src/cs/drivers/drv_app/ffs/board/cfgffs.c	Sun Oct 02 07:44:36 2016 +0000
+++ b/src/cs/drivers/drv_app/ffs/board/cfgffs.c	Sun Oct 02 08:10:40 2016 +0000
@@ -16,6 +16,7 @@
 #include "ffs/board/drv.h"
 
 #include "config/board.cfg"
+#include "config/fc-target.cfg"
 
 #if (BOARD == 34)
   #include "ffs/board/ffspcm.h"
@@ -56,6 +57,13 @@
 
 #else
 
+#if defined(CONFIG_TARGET_PIRELLI) || defined(CONFIG_TARGET_FCFAM)
+
+uint16 ffs_flash_manufact = MANUFACT_AMD;
+uint16 ffs_flash_device   = 0x2101;
+
+#else
+
 uint16 ffs_flash_manufact = 0x00; // autodetect device
 //uint16 ffs_flash_manufact = MANUFACT_RAM;
 //uint16 ffs_flash_manufact = 0x04; // Fujitsu
@@ -67,6 +75,8 @@
 //uint16 ffs_flash_device   = 0x2761; // SST device 1601
 //uint16 ffs_flash_device   = 0x2259; // 8x8kB blocks
 
+#endif
+
 int ffs_ram_image_address = 0;  // Dummy
 
 //unsigned char ffs_image[8*8*1024];

--- a/src/cs/drivers/drv_app/ffs/board/dev.c	Sun Oct 02 07:44:36 2016 +0000
+++ b/src/cs/drivers/drv_app/ffs/board/dev.c	Sun Oct 02 08:10:40 2016 +0000
@@ -12,6 +12,7 @@
 #include "ffs/board/drv.h" 
 #include "config/board.cfg"
 #include "config/rf.cfg"
+#include "config/fc-target.cfg"
 
 /******************************************************************************
 
@@ -88,6 +89,44 @@
 // Note that does NOT support a flash definition with different sized blocks
 // so all blocks contained in the device definition MUST be the same size!
 
+#if defined(CONFIG_TARGET_PIRELLI) || defined(CONFIG_TARGET_FCFAM)
+// 256 KiB sectors
+static const struct block_info_s flash_32x256[] =
+{
+  { 0x000000, 18 },
+  { 0x040000, 18 },
+  { 0x080000, 18 },
+  { 0x0C0000, 18 },
+  { 0x100000, 18 },
+  { 0x140000, 18 },
+  { 0x180000, 18 },
+  { 0x1C0000, 18 },
+  { 0x200000, 18 },
+  { 0x240000, 18 },
+  { 0x280000, 18 },
+  { 0x2C0000, 18 },
+  { 0x300000, 18 },
+  { 0x340000, 18 },
+  { 0x380000, 18 },
+  { 0x3C0000, 18 },
+  { 0x400000, 18 },
+  { 0x440000, 18 },
+  { 0x480000, 18 },
+  { 0x4C0000, 18 },
+  { 0x500000, 18 },
+  { 0x540000, 18 },
+  { 0x580000, 18 },
+  { 0x5C0000, 18 },
+  { 0x600000, 18 },
+  { 0x640000, 18 },
+  { 0x680000, 18 },
+  { 0x6C0000, 18 },
+  { 0x700000, 18 },
+  { 0x740000, 18 },
+  { 0x780000, 18 },
+  { 0x7C0000, 18 }
+};
+#endif
 
 // 128x64kb
 static const struct block_info_s flash_128x64[] =
@@ -316,6 +355,22 @@
 
     /********** AMD Devices ***********************************************/
 
+#ifdef CONFIG_TARGET_PIRELLI
+    // Spansion S71PL129NC0 used in Pirelli DP-L10
+    // ID made up (same as what Pirelli's fw uses), not using autodetect
+    // This is an aftermarket FFS config for the Pirelli target
+    { &flash_32x256[0], (char *) 0x02480000, MANUFACT_AMD,     0x2101,
+      FFS_DRIVER_AMD,  6 },
+#endif
+
+#ifdef CONFIG_TARGET_FCFAM
+    // We plan on using the same flash+pSRAM chip in our own
+    // FreeCalypso hardware designs, but on a different chip select.
+    // Let's use the first 2 MiB of the 2nd bank for the FFS.
+    { &flash_32x256[0], (char *) 0x01800000, MANUFACT_AMD,     0x2101,
+      FFS_DRIVER_AMD,  8 },
+#endif
+
 	// AMD Am29DL640F. Ignoring the 8kB sectors
     // Multi-id device: 0x227E, 0x2221, 0x2200. Converted to 0x2100
     { &flash_16x64[0], (char *) 0x01800000, MANUFACT_AMD,     0x2100,
@@ -421,8 +476,14 @@
       FFS_DRIVER_INTEL_SB,  6 },
 
     // Intel 28F320C3-T, 32Mb. Using top-most 8x8kB (parameter) sectors.
+#ifdef CONFIG_TARGET_C139
+    // Changed for C139 aftermarket FFS config: 64x3 at 0x3C0000
+    { &flash_16x64[0], (char *) 0x3C0000, MANUFACT_INTEL,   0x88C4,
+      FFS_DRIVER_INTEL_SB,  3 },
+#else
     { &flash_8x8[0],   (char *) 0x3F0000, MANUFACT_INTEL,   0x88C4,
       FFS_DRIVER_INTEL_SB,  8 },
+#endif
 
     // Intel 28F320C3-B, 32Mb. Using top-most 8x64kB sectors
     { &flash_16x64[0], (char *) 0x380000, MANUFACT_INTEL,   0x88C5,

--- a/src/cs/drivers/drv_app/ffs/board/drv.c	Sun Oct 02 07:44:36 2016 +0000
+++ b/src/cs/drivers/drv_app/ffs/board/drv.c	Sun Oct 02 08:10:40 2016 +0000
@@ -244,7 +244,7 @@
 
 void ffsdrv_amd_write_halfword(volatile uint16 *addr, uint16 value)
 {
-    volatile char *flash = dev.base;
+    volatile uint16 *flash = (volatile uint16 *)dev.base;
     uint32 cpsr;
 
     tlw(led_on(LED_WRITE));
@@ -261,9 +261,9 @@
     cpsr = int_disable();
     tlw(led_toggle(LED_WRITE_SUSPEND));
     dev.state = DEV_WRITE;
-    flash[0xAAAA] = 0xAA; // unlock cycle 1
-    flash[0x5555] = 0x55; // unlock cycle 2
-    flash[0xAAAA] = 0xA0;
+    flash[0x555] = 0xAA; // unlock cycle 1
+    flash[0x2AA] = 0x55; // unlock cycle 2
+    flash[0x555] = 0xA0;
     *addr         = value;
     int_enable(cpsr);
     tlw(led_toggle(LED_WRITE_SUSPEND));
@@ -306,7 +306,7 @@
 
 void ffsdrv_amd_erase(uint8 block)
 {
-    volatile char *flash = dev.base;
+    volatile uint16 *flash = (volatile uint16 *)dev.base;
     uint32 cpsr;
 
     tlw(led_on(LED_ERASE));
@@ -316,11 +316,11 @@
 
     cpsr = int_disable();
     dev.state = DEV_ERASE;
-    flash[0xAAAA] = 0xAA; // unlock cycle 1
-    flash[0x5555] = 0x55; // unlock cycle 2
-    flash[0xAAAA] = 0x80; 
-    flash[0xAAAA] = 0xAA; // unlock cycle 1
-    flash[0x5555] = 0x55; // unlock cycle 2
+    flash[0x555] = 0xAA; // unlock cycle 1
+    flash[0x2AA] = 0x55; // unlock cycle 2
+    flash[0x555] = 0x80; 
+    flash[0x555] = 0xAA; // unlock cycle 1
+    flash[0x2AA] = 0x55; // unlock cycle 2
     *dev.addr = 0x30; // AMD erase sector command
     int_enable(cpsr);