comparison src/cs/system/Main/init.c @ 407:f7f1f6f1a77d

init.c module: a chance at being correct for the D-Sample target
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 18 Jan 2018 04:45:11 +0000
parents 840113655bbf
children 706f4b71aceb
comparison
equal deleted inserted replaced
406:d926a8986755 407:f7f1f6f1a77d
496 /* 496 /*
497 * The following part has been reconstructed from disassembly. 497 * The following part has been reconstructed from disassembly.
498 */ 498 */
499 RHEA_INITRHEA(0,0,0xFF); 499 RHEA_INITRHEA(0,0,0xFF);
500 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1); 500 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
501 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8); 501 #if (CHIPSET == 8)
502 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6);
503 #elif (CHIPSET == 10)
504 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
505 #else
506 #error "We only have DPLL setup for CHIPSETs 8 and 10"
507 #endif
502 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */ 508 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
503 /* 509 /*
504 * FreeCalypso change: memory timings and widths 510 * FreeCalypso change: memory timings and widths
505 * are target-dependent. 511 * are target-dependent.
506 */ 512 */
512 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0); 518 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
513 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0); 519 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
514 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); 520 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
515 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); 521 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
516 MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0); 522 MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0);
517 #elif defined(CONFIG_TARGET_FCFAM) 523 #elif defined(CONFIG_TARGET_FCFAM) || defined(CONFIG_TARGET_DSAMPLE)
518 /* 524 /*
519 * The settings currently adopted for the FreeCalypso 525 * The settings currently adopted for the FreeCalypso
520 * hardware family, only nCS0, nCS1 and nCS2 are used 526 * hardware family, only nCS0, nCS1 and nCS2 are used
521 * presently. 527 * presently.
522 */ 528 */
745 /* 751 /*
746 * FreeCalypso change: this write is only correct when running 752 * FreeCalypso change: this write is only correct when running
747 * on an actual D-Sample board, but not on any of the real-world 753 * on an actual D-Sample board, but not on any of the real-world
748 * Calypso target devices. 754 * Calypso target devices.
749 */ 755 */
750 #if 0 756 #ifdef CONFIG_TARGET_DSAMPLE
751 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000; 757 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
752 #endif 758 #endif
753 #endif // BOARD 759 #endif // BOARD
754 760
755 // Enable HW Timers 1 & 2 761 // Enable HW Timers 1 & 2