FreeCalypso > hg > fc-magnetite
changeset 407:f7f1f6f1a77d
init.c module: a chance at being correct for the D-Sample target
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Thu, 18 Jan 2018 04:45:11 +0000 |
| parents | d926a8986755 |
| children | 336edc558a30 |
| files | src/cs/system/Main/init.c |
| diffstat | 1 files changed, 9 insertions(+), 3 deletions(-) [+] |
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--- a/src/cs/system/Main/init.c Thu Jan 18 04:29:50 2018 +0000 +++ b/src/cs/system/Main/init.c Thu Jan 18 04:45:11 2018 +0000 @@ -498,7 +498,13 @@ */ RHEA_INITRHEA(0,0,0xFF); DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1); - DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8); + #if (CHIPSET == 8) + DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6); + #elif (CHIPSET == 10) + DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8); + #else + #error "We only have DPLL setup for CHIPSETs 8 and 10" + #endif CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */ /* * FreeCalypso change: memory timings and widths @@ -514,7 +520,7 @@ MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0); - #elif defined(CONFIG_TARGET_FCFAM) + #elif defined(CONFIG_TARGET_FCFAM) || defined(CONFIG_TARGET_DSAMPLE) /* * The settings currently adopted for the FreeCalypso * hardware family, only nCS0, nCS1 and nCS2 are used @@ -747,7 +753,7 @@ * on an actual D-Sample board, but not on any of the real-world * Calypso target devices. */ - #if 0 + #ifdef CONFIG_TARGET_DSAMPLE *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000; #endif #endif // BOARD