--- a/src/cs/drivers/drv_app/uart/uartfax.c	Sun Oct 02 05:37:13 2016 +0000
+++ b/src/cs/drivers/drv_app/uart/uartfax.c	Sun Oct 02 06:23:18 2016 +0000
@@ -89,6 +89,8 @@
 #include "btemobile.cfg"
 #endif
 
+#include "fc-target.cfg"
+
 
 #include <string.h>
 #include "nucleus.h"
@@ -553,7 +555,7 @@
     SYS_UWORD8 rts_level; /* RTS on RS232 side, CTS on chipset side.
                              1: The RS232 line is deactivated (low). */
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
     SYS_UWORD8 dtr_level; /* Controlled with an I/O on C & D-Sample and
                              handled by Calypso+ on E-Sample.
                              1: The RS232 line is deactivated (low). */
@@ -915,7 +917,7 @@
      * lose events detected in the RX interrupt handler.
      */
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
     if (call_source == 3) /* Call from Rx HISR */
         dtr_level = uart->dtr_level_saved[uart->index_hisr];
     else
@@ -932,7 +934,7 @@
 
     state |= ((((SYS_UWORD32) uart->rts_level) << RTS) |
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
               (((SYS_UWORD32) dtr_level) << DTR) |
 #endif
 
@@ -955,7 +957,7 @@
      * DTR is supported on C, D & E-Sample.
      */
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
     state |= (((SYS_UWORD32) uart->dtr_level) << SA);
 #endif
 
@@ -1965,7 +1967,7 @@
     SER_restart_uart_sleep_timer ();
     uart_sleep_timer_enabled = 1;
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
     uart->index_hisr = (uart->index_hisr + 1) & 0x01; /* 0 or 1 */
 #endif
 
@@ -2166,7 +2168,7 @@
              (uart->rd_call_setup == rm_reInstall))) {
 
             if ((bytes_in_rx_buffer >= uart->rx_threshold_level) ||
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
                 uart->dtr_change_detected[uart->index_hisr] ||
 #endif
                 uart->break_received ||
@@ -2179,7 +2181,7 @@
                 uart->reading_suspended = 0;
                 uart->break_received = 0;
                 uart->esc_seq_received = 0;
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
                 uart->dtr_change_detected[uart->index_hisr] = 0;
 #endif
             }
@@ -2592,7 +2594,9 @@
         else {
             
             uart->tx_stopped_by_driver = 0;
-            LowGPIO(1);
+            #ifdef CONFIG_TARGET_GTAMODEM
+                AI_ResetBit(1);
+            #endif
 
 #if ((CHIPSET != 5) && (CHIPSET != 6))
             /*
@@ -2999,7 +3003,7 @@
     else
         uart->rts_level = 1;
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41))
+#if UARTFAX_CLASSIC_DTR_DCD
     /*
      * On C & D-Sample, 2 I/O are used to control DCD and DTR on UART Modem.
      * DCD: I/O 2 (output)
@@ -3219,7 +3223,7 @@
 
     WRITE_UART_REGISTER (uart, IER, 0x00);
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41))
+#if UARTFAX_CLASSIC_DTR_DCD
     AI_MaskIT (ARMIO_MASKIT_GPIO);
 #elif (CHIPSET == 12)
     DISABLE_DSR_INTERRUPT (uart);
@@ -3360,7 +3364,7 @@
     else
         uart->rts_level = 1;
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41))
+#if UARTFAX_CLASSIC_DTR_DCD
     /*
      * Read the state of DTR and select the edge.
      */
@@ -4322,8 +4326,10 @@
 
 	/* If we have been stopped due to high RTS, we have to
 	 * wake up application processor by IRQ via IO1 -HW */
-	if (uart->tx_stopped_by_driver)
-            HighGPIO(1);
+	#ifdef CONFIG_TARGET_GTAMODEM
+	    if (uart->tx_stopped_by_driver)
+		AI_SetBit(1);
+	#endif
 
         /*
          * If:
@@ -4544,7 +4550,7 @@
 
         *state |= ((((SYS_UWORD32) uart->rts_level) << RTS) |
         
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
                    (((SYS_UWORD32) uart->dtr_level) << DTR) |
 #endif
 
@@ -4568,7 +4574,7 @@
          * DTR is supported on C, D & E-Sample.
          */
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
         *state |= (((SYS_UWORD32) uart->dtr_level) << SA);
 #endif
 
@@ -4639,7 +4645,7 @@
      * DSR is not supported on all platforms.
      */
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
     if (mask & (1 << SA))
 #else
     if ((mask & (1 << SA)) || (mask & (1 << DCD)))
@@ -4741,7 +4747,7 @@
      * The DCD field is ignored if the SB bit of the mask is set.
      */
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
 
     if (!(mask & (1 << SB)) && (mask & (1 << DCD))) {
 
@@ -4777,7 +4783,7 @@
      * DCD is supported on C, D & E-Sample.
      */
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
 
     if (mask & (1 << SB)) {
 
@@ -4883,7 +4889,7 @@
 
     case RX_DATA:
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12))
+#if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
         uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */
         uart->dtr_change_detected[uart->index_it] = 0;
         uart->dtr_level_saved[uart->index_it] = uart->dtr_level;
@@ -5017,7 +5023,7 @@
     return (result);
 }
 
-#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41))
+#if UARTFAX_CLASSIC_DTR_DCD
 /*******************************************************************************
  *
  *                              UAF_DTRInterruptHandler