FreeCalypso > hg > fc-magnetite
changeset 417:706f4b71aceb
more sensible MEMIF setup for D-Sample C05 target
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sat, 20 Jan 2018 18:56:35 +0000 |
| parents | 5ca341a26dda |
| children | f9e7fac0b437 |
| files | src/cs/system/Main/init.c |
| diffstat | 1 files changed, 13 insertions(+), 1 deletions(-) [+] |
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--- a/src/cs/system/Main/init.c Sat Jan 20 00:37:48 2018 +0000 +++ b/src/cs/system/Main/init.c Sat Jan 20 18:56:35 2018 +0000 @@ -520,7 +520,7 @@ MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0); - #elif defined(CONFIG_TARGET_FCFAM) || defined(CONFIG_TARGET_DSAMPLE) + #elif defined(CONFIG_TARGET_FCFAM) /* * The settings currently adopted for the FreeCalypso * hardware family, only nCS0, nCS1 and nCS2 are used @@ -531,6 +531,18 @@ MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0); + #elif defined(CONFIG_TARGET_DSAMPLE) && (CHIPSET == 8) + /* + * On D-Sample C05 (older Calypso silicon version) the clocks + * run slower: the ARM clock runs at 39 MHz instead of 52 MHz. + * Therefore, we need to use fewer wait states to effect + * the same memory speed. + */ + MEM_INIT_CS0(2, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS1(2, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS2(2, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS3(2, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); #else /* * The original settings from Openmoko,