FreeCalypso > hg > fc-magnetite
changeset 267:f62b71017afd
init.c: initial preen at the module level
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sun, 06 Aug 2017 08:57:26 +0000 |
| parents | 692f565226ef |
| children | f5c10ec9c5fd |
| files | src/cs/system/Main/init.c |
| diffstat | 1 files changed, 5 insertions(+), 1110 deletions(-) [+] |
line wrap: on
line diff
--- a/src/cs/system/Main/init.c Sat Aug 05 02:11:22 2017 +0000 +++ b/src/cs/system/Main/init.c Sun Aug 06 08:57:26 2017 +0000 @@ -11,14 +11,6 @@ /* Config Files */ -#pragma DUPLICATE_FOR_INTERNAL_RAM_START - -#ifndef PSP_FAILSAFE -#define PSP_FAILSAFE 0 -#warn "PSP Failsafe Flag Not Defined in your Build, taking default" -#endif - - #ifndef _WINDOWS #include "l1sw.cfg" #include "rf.cfg" @@ -55,7 +47,6 @@ #include "l1_types.h" #include "l1_confg.h" #include "l1_const.h" -#include "pin_config.h" // added for Init tuned to Power Management #if TESTMODE #include "l1tm_defty.h" @@ -119,47 +110,13 @@ #include "armio/armio.h" #include "timer/timer.h" -#if (CHIPSET==15) -#include "types.h" -#include "bspI2c.h" -#include "bspTwl3029.h" -#include "bspTwl3029_I2c.h" -#include "bspTwl3029_Power.h" -#if (OP_L1_STANDALONE == 0) - #include "uicc/board/bspUicc.h" -#endif -#endif - #if (OP_L1_STANDALONE == 0) #include "rvf/rvf_api.h" #include "rvm/rvm_api.h" /* A-M-E-N-D-E-D! */ #include "sim/sim.h" #endif -#include "dynamic_clock.h" -#if (ANLG_FAM !=11) #include "abb/abb.h" -#endif - -#if (BOARD==35 || BOARD==46) - #if (OP_L1_STANDALONE == 0) - #include "csmi/csmi.h" - #include "csmi/csmi_gsmctrl.h" - #include "csmi/csmi_uart.h" - #include "uart/uartfax.h" - #include "csmi/csmi_uartfax.h" - #include "ffs/ffs.h" - #include "ffs/ffspcm.h" - #include "csmi/sleep.h" - #endif /* (OP_L1_STANDALONE == 0) */ -#endif - -/* WCP Profiler */ -#if (BOARD==35 || BOARD==43 || BOARD==46) && (OP_L1_STANDALONE == 0) - #if WCP_PROF == 1 - #include "prf/prf_api.h" - #endif -#endif #include "inth/iq.h" #include "tpudrv.h" @@ -167,16 +124,12 @@ #include "clkm/clkm.h" #include "inth/inth.h" -#if (OP_L1_STANDALONE == 0) - void bspUicc_Phy_intCHandler(void); +#if (OP_L1_STANDALONE == 1) + #include "uart/serialswitch_core.h" +#else + #include "uart/serialswitch.h" #endif - - #if (OP_L1_STANDALONE == 1) - #include "uart/serialswitch_core.h" - #else - #include "uart/serialswitch.h" - #endif - #include "uart/traceswitch.h" +#include "uart/traceswitch.h" #include "dma/dma.h" @@ -184,42 +137,6 @@ #include "ulpd/ulpd.h" -#if (PSP_STANDALONE == 0) - #if (GSM_IDLE_RAM != 0) - #if (OP_L1_STANDALONE == 1) - #include "csmi_simul.h" - #else - #include "csmi/csmi.h" - #endif - #endif -#endif - -#if (CHIPSET == 12) || (CHIPSET == 15) || ((CHIPSET == 10) && (OP_WCP == 1)) - #include "memif/sys_memif.h" -#endif - -#if ((CHIPSET == 12) || (CHIPSET == 15)) - #include "timer/timer_sec.h" - #include "dma/sys_dma.h" - #include "conf/sys_conf.h" - #include "inth/sys_inth.h" - #ifdef RVM_NAN_SWE - #include "nan/nan_i.h" - #endif - #ifdef RVM_DMA_SWE - #include "dma/board/dma_inth.h" - #endif - #ifdef RVM_I2C_SWE - #include "i2c/i2c_hw_functions.h" - #endif - #ifdef RVM_MC_SWE - #include "mc/board/mc_inth.h" - #endif - #ifdef RVM_USB_SWE - #include "usb/usb_inth.h" - #endif -#endif - #if (OP_L1_STANDALONE == 0) #define TIMER_RESET_VALUE (0xFFFF) @@ -232,7 +149,6 @@ #define LIMIT_FOR_L1_SYNC (80) #endif -UWORD16 flash_device_id; #if (PSP_STANDALONE == 0) #if (OP_L1_STANDALONE == 0) extern void ffs_main_init(void); @@ -253,137 +169,6 @@ #endif /* (OP_L1_STANDALONE) */ #endif -#if (CHIPSET == 12) || (CHIPSET == 15) -extern const T_INTH_CONFIG a_inth_config[C_INTH_NB_INTERRUPT]; -#ifdef RVM_CAMD_SWE -extern void f_camera_interrupt_manager(void); -#endif -#endif - -#if (GSM_IDLE_RAM != 0) - #if (CHIPSET == 12) || (CHIPSET == 15) - - // Interrupt handler called in case the interrupt requires the traffic controler active - // These routines need to be declared here in order to put them into the a_inth_config_idle_ram structure - extern void ext_ram_irq_inth_handler(void); - extern void ext_ram_fiq_inth_handler(void); - - - - // declared for the _intram file generated by ICL470 - extern const T_INTH_CONFIG a_inth_config_idle_ram[C_INTH_NB_INTERRUPT]; - - // Debug mode: irq ext shall be connected to the chipselect signals - #if GSM_IDLE_RAM_DEBUG - extern void flash_access_handler(void); - extern void ext_ram_access_handler(void); - #endif - #endif // CHIPSET 12 || CHIPSET 15 -#endif - -#if (PSP_STANDALONE == 0) - extern void hisr(void); - extern void layer_1_sync_HISR_entry(void); - - extern NU_HISR layer_1_sync_HISR; - - #if (CODE_VERSION != SIMULATION) - #if (BOARD == 71) - extern void INT_DisableIRQ(void); - extern void INT_EnableIRQ(void); - #endif /* (BOARD == 71) */ - #endif /* CODE_VERSION != SIMULATION */ - -#if (LOCOSTO_LITE==1) -#ifndef HISR_STACK_SHARING -#define HISR_STACK_SHARING -#endif -#endif - -#ifdef HISR_STACK_SHARING -unsigned char HISR_STACK_PRIO2[1500]={0xFE}; -#endif - -#if (OP_L1_STANDALONE == 0) - #pragma DATA_SECTION(layer_1_sync_stack,".stackandheap"); - #define LAYER_1_SYNC_STACK_SIZE (3000 /*4000*/) - extern unsigned char layer_1_sync_stack[LAYER_1_SYNC_STACK_SIZE]; - #else - #if (LONG_JUMP == 3) - #pragma DATA_SECTION(layer_1_sync_stack,".HISR_stack"); - #endif - - #if TESTMODE - extern char FAR layer_1_sync_stack[2600 /*3600*/]; // Frame interrupt task stack for EVA3 - #else - extern char FAR layer_1_sync_stack[1600 /*2600*/]; // Frame interrupt task stack for EVA3 - #endif - #endif /* OP_L1_STANDALONE */ - -#if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1) - extern void api_modem_hisr(); -#if (LONG_JUMP == 3) - #pragma DATA_SECTION(API_MODEM_HISR_stack,".l1s_global"); -#endif - extern char FAR API_MODEM_HISR_stack[0x400]; // stack size to be tuned - extern NU_HISR api_modemHISR; -#endif - - #pragma DUPLICATE_FOR_INTERNAL_RAM_END - - #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) - #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START - #if (OP_L1_STANDALONE == 0) - /* - * Timing monitor - * - * - */ - #if (TRACE_TYPE == 4) - extern T_L1A_L1S_COM l1a_l1s_com; - extern T_L1S_GLOBAL l1s; - UNSIGNED max_cpu, fn_max_cpu; - unsigned short layer_1_sync_end_time; - unsigned short max_cpu_flag; - #endif - #endif - #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END - #endif // !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) - - #if (L1_EXT_AUDIO_MGT == 1) - NU_HISR EXT_AUDIO_MGT_hisr; - #ifndef HISR_STACK_SHARING - char FAR ext_audio_mgt_hisr_stack[500]; - #else - #define ext_audio_mgt_hisr_stack HISR_STACK_PRIO2 - #endif - extern void Cust_ext_audio_mgt_hisr(void); - #endif - -#if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) ) // equivalent to an API_HISR flag - extern void api_hisr(void); - #ifndef HISR_STACK_SHARING - #if (LONG_JUMP == 3) - #pragma DATA_SECTION (API_HISR_stack,".l1s_global"); - #endif - - char FAR API_HISR_stack[0x400]; - #else - #define API_HISR_stack HISR_STACK_PRIO2 - #endif - NU_HISR apiHISR; - #endif // (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_DYN_DSP_DWNLD == 1) - -#if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1) - #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM != 0)) - #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START - char FAR API_MODEM_HISR_stack[0x400]; // stack size to be tuned - NU_HISR api_modemHISR; - #pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END - #endif -#endif // FF_L1_IT_DSP_USF -#endif /* PSP_STANDALONE == 0 */ - #if (OP_L1_STANDALONE == 1) #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) || TESTMODE) #include "uart/uart.h" @@ -418,7 +203,6 @@ #else T_AppliSerialInfo appli_ser_cfg_info = #endif /* OP_L1_STANDALONE */ - #if (CHIPSET!=15) { #ifdef BTEMOBILE #ifdef BT_UART_USED_MODEM @@ -504,406 +288,9 @@ DUMMY_TRACE} // 0x0168 } }; - #else /* CHIPSET==15 */ - { - {DUMMY_BT_HCI, - DUMMY_FAX_DATA, - UART_IRDA_TRACE, - DUMMY_TRACE}, // 0x0148 - 3, - { - {DUMMY_BT_HCI, - DUMMY_FAX_DATA, - UART_IRDA_TRACE, - DUMMY_TRACE},// 0x0148 - {DUMMY_BT_HCI, - DUMMY_FAX_DATA, - DUMMY_TRACE, - UART_IRDA_TRACE}, // 0x1048 - {UART_IRDA_BT_HCI, - DUMMY_FAX_DATA, - DUMMY_TRACE, - DUMMY_TRACE}, // 0x0049 - } - }; - #endif /* CHIPSET !=15*/ #endif /* (TRACE_TYPE ...) || (OP_L1_STANDALONE == 0) */ -#if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) -#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START - -#if (PSP_STANDALONE == 0) -/* - * HISR stack and semaphore needed by L1 - */ - -#if (OP_L1_STANDALONE == 0) - unsigned char layer_1_sync_stack[LAYER_1_SYNC_STACK_SIZE]; -#else - #if TESTMODE - char FAR layer_1_sync_stack[2600 /*3600*/]; // Frame interrupt task stack for EVA3 - #else - char FAR layer_1_sync_stack[1600 /* 2600 */]; // Frame interrupt task stack for EVA3 - #endif -#endif /* OP_L1_STANDALONE */ - -NU_HISR layer_1_sync_HISR; // Frame interrupt task stack for EVA3 -#endif - -#if (CHIPSET == 12) - - const T_INTH_CONFIG a_inth_config[C_INTH_NB_INTERRUPT] = - { // IRQ/FIQ LEVEL/EDGE PRIORITY HANDLER - { C_INTH_IRQ, C_INTH_EDGE, 0x01, IQ_TimerHandler }, // 0 : WATCHDOG TIMER - { C_INTH_IRQ, C_INTH_EDGE, 0x02, IQ_TimerHandler1 }, // 1 : TIMER 1 - { C_INTH_IRQ, C_INTH_EDGE, 0x02, IQ_TimerHandler2 }, // 2 : TIMER 2 - { C_INTH_FIQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 3 : TSP RECEIVE - { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_FrameHandler }, // 4 : TPU FRAME - { C_INTH_IRQ, C_INTH_EDGE, 0x04, f_inth_dummy }, // 5 : TPU PAGE - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 6 : SIM - #else - { C_INTH_IRQ, C_INTH_EDGE, 0x07, SIM_IntHandler }, // 6 : SIM - #endif - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, SER_uart_modem_handler }, // 7 : UART_MODEM1 - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, f_inth_dummy }, // 8 : KEYBOARD - #else - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, IQ_KeypadHandler }, // 8 : KEYBOARD - #endif - { C_INTH_IRQ, C_INTH_EDGE, 0x03, IQ_Rtc_Handler }, // 9 : RTC_TIMER - { C_INTH_IRQ, C_INTH_LEVEL, 0x03, IQ_RtcA_Handler }, // 10 : RTC_ALARM - { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_Gauging_Handler }, // 11 : ULPD_GAUGING - { C_INTH_IRQ, C_INTH_EDGE, 0x08, IQ_External }, // 12 : ABB_IRQ - { C_INTH_IRQ, C_INTH_EDGE, 0x05, f_inth_dummy }, // 13 : SPI - { C_INTH_IRQ, C_INTH_LEVEL, 0x06, f_dma_interrupt_manager }, // 14 : DMA - { C_INTH_IRQ, C_INTH_EDGE, 0x03, IQ_ApiHandler }, // 15 : API - { C_INTH_IRQ, C_INTH_EDGE, 0x07, f_inth_dummy }, // 16 : GPIO - { C_INTH_FIQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 17 : ABB_FIQ - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, SER_uart_irda_handler }, // 18 : UART_IRDA - { C_INTH_IRQ, C_INTH_LEVEL, 0x03, IQ_GsmTim_Handler }, // 19 : ULPD GSM TIMER - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 20 : GEA -#if GSM_IDLE_RAM_DEBUG - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, flash_access_handler }, // 21 : EXTERNAL IRQ 1 - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_access_handler }, // 22 : EXTERNAL IRQ 2 -#else - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 21 : EXTERNAL IRQ 1 - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 22 : EXTERNAL IRQ 2 -#endif - #if (OP_L1_STANDALONE == 0) - { C_INTH_FIQ, C_INTH_LEVEL, 0x02, bspUicc_Phy_intCHandler }, // 23 : USIM Card Detect - { C_INTH_IRQ, C_INTH_EDGE, 0x02, bspUicc_Phy_intCHandler }, // 24 : USIM - #else - { C_INTH_FIQ, C_INTH_LEVEL, 0x02, f_inth_dummy }, // 23 : USIM Card Detect - { C_INTH_IRQ, C_INTH_EDGE, 0x02, f_inth_dummy }, // 24 : USIM - #endif - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 25 : LCD - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 26 : USB - #else - #ifdef RVM_USB_SWE - { C_INTH_IRQ, C_INTH_LEVEL, 0x00, usb_int_handler }, // 26 : USB - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, - #endif - #endif - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 27 : MMC/SD/MS - #else - #ifdef RVM_MC_SWE - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, mc_int_handler }, // 27 : MMC/SD/MS - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, - #endif - #endif - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, SER_uart_modem2_handler }, // 28 : UART_MODEM2 - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_2nd_level_handler }, // 29 : 2nd Interrupt Handler - #else - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, f_inth_2nd_level_handler }, // 29 : 2nd Interrupt Handler - #endif - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 30 : I2C - #else - #ifdef RVM_I2C_SWE - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, i2c_hw_int_manager }, // 30 : I2C - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, - #endif - #endif - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 31 : NAND FLASH - #else - #ifdef RVM_NAN_SWE - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, nan_IT_handler }, // 31 : NAND FLASH - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, - #endif - #endif - - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 0 : RNG - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 1 : SHA1/MD5 - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 2 : EMPU - { C_INTH_IRQ, C_INTH_LEVEL, 0x06, f_dma_interrupt_manager }, // 14 : DMA - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy } // 4 : Secure TIMER - }; - -#if (GSM_IDLE_RAM != 0) - const T_INTH_CONFIG a_inth_config_idle_ram[C_INTH_NB_INTERRUPT] = - { // IRQ/FIQ LEVEL/EDGE PRIORITY HANDLER - { C_INTH_IRQ, C_INTH_EDGE, 0x01, ext_ram_irq_inth_handler }, // 0 : WATCHDOG TIMER - { C_INTH_IRQ, C_INTH_EDGE, 0x02, ext_ram_irq_inth_handler }, // 1 : TIMER 1 - { C_INTH_IRQ, C_INTH_EDGE, 0x02, ext_ram_irq_inth_handler }, // 2 : TIMER 2 - { C_INTH_FIQ, C_INTH_EDGE, 0xFF, ext_ram_fiq_inth_handler }, // 3 : TSP RECEIVE - { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_FrameHandler }, // 4 : TPU FRAME - { C_INTH_IRQ, C_INTH_EDGE, 0x04, ext_ram_irq_inth_handler }, // 5 : TPU PAGE - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, ext_ram_irq_inth_handler }, // 6 : SIM - #else - { C_INTH_IRQ, C_INTH_EDGE, 0x07, ext_ram_irq_inth_handler }, // 6 : SIM - #endif - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, ext_ram_irq_inth_handler }, // 7 : UART_MODEM1 - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_irq_inth_handler }, // 8 : KEYBOARD - #else - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_irq_inth_handler }, // 8 : KEYBOARD - #endif - { C_INTH_IRQ, C_INTH_EDGE, 0x03, ext_ram_irq_inth_handler }, // 9 : RTC_TIMER - { C_INTH_IRQ, C_INTH_LEVEL, 0x03, ext_ram_irq_inth_handler }, // 10 : RTC_ALARM - { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_Gauging_Handler }, // 11 : ULPD_GAUGING - { C_INTH_IRQ, C_INTH_EDGE, 0x08, ext_ram_irq_inth_handler }, // 12 : ABB_IRQ - { C_INTH_IRQ, C_INTH_EDGE, 0x05, ext_ram_irq_inth_handler }, // 13 : SPI - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0x06, ext_ram_irq_inth_handler }, // 14 : DMA - #else - { C_INTH_IRQ, C_INTH_EDGE, 0x02, ext_ram_irq_inth_handler }, // 14 : DMA - #endif - { C_INTH_IRQ, C_INTH_EDGE, 0x03, ext_ram_irq_inth_handler }, // 15 : API - { C_INTH_IRQ, C_INTH_EDGE, 0x07, ext_ram_irq_inth_handler }, // 16 : GPIO - { C_INTH_FIQ, C_INTH_EDGE, 0xFF, ext_ram_fiq_inth_handler }, // 17 : ABB_FIQ - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, ext_ram_irq_inth_handler }, // 18 : UART_IRDA - { C_INTH_IRQ, C_INTH_LEVEL, 0x03, IQ_GsmTim_Handler }, // 19 : ULPD GSM TIMER - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 20 : GEA -#if GSM_IDLE_RAM_DEBUG - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, flash_access_handler }, // 21 : EXTERNAL IRQ 1 - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_access_handler }, // 22 : EXTERNAL IRQ 2 -#else - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 21 : EXTERNAL IRQ 1 - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 22 : EXTERNAL IRQ 2 -#endif - { C_INTH_FIQ, C_INTH_LEVEL, 0xFF, ext_ram_fiq_inth_handler }, // 23 : USIM Card Detect - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, ext_ram_irq_inth_handler }, // 24 : USIM - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 25 : LCD - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 26 : USB - #else - { C_INTH_IRQ, C_INTH_LEVEL, 0x00, ext_ram_irq_inth_handler }, // 26 : USB - #endif - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 27 : MMC/SD/MS - #else - #ifdef RVM_MC_SWE - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, ext_ram_irq_inth_handler }, // 27 : MMC/SD/MS - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, ext_ram_irq_inth_handler }, - #endif - #endif - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, ext_ram_irq_inth_handler }, // 28 : UART_MODEM2 - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 29 : 2nd Interrupt Handler - #else - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, ext_ram_irq_inth_handler }, // 29 : 2nd Interrupt Handler - #endif - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 30 : I2C - #else - { C_INTH_IRQ, C_INTH_EDGE, 0x01, ext_ram_irq_inth_handler }, // 30 : I2C - #endif - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 31 : NAND FLASH - #else - { C_INTH_IRQ, C_INTH_EDGE, 0x02, ext_ram_irq_inth_handler }, // 31 : NAND FLASH - #endif - - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 0 : RNG - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 1 : SHA1/MD5 - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 2 : EMPU - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler }, // 3 : Secure DMA - #else - { C_INTH_IRQ, C_INTH_LEVEL, 0x03, ext_ram_irq_inth_handler }, // 3 : Secure DMA - #endif - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, ext_ram_irq_inth_handler } // 4 : Secure TIMER - }; -#endif //(GSM_IDLE_RAM != 0) - -#endif /* (CHIPSET ==12) */ - -#if (CHIPSET == 15) - const T_INTH_CONFIG a_inth_config[C_INTH_NB_INTERRUPT] = - { // IRQ/FIQ LEVEL/EDGE PRIORITY HANDLER - { C_INTH_IRQ, C_INTH_EDGE, 0x01, IQ_TimerHandler }, // 0 : WATCHDOG TIMER - { C_INTH_IRQ, C_INTH_EDGE, 0x02, IQ_TimerHandler1 }, // 1 : TIMER 1 - { C_INTH_IRQ, C_INTH_EDGE, 0x02, IQ_TimerHandler2 }, // 2 : TIMER 2 - { C_INTH_FIQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 3 : MCSI - #if (PSP_STANDALONE == 0) - { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_FrameHandler }, // 4 : TPU FRAME - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 4 : TPU FRAME - #endif - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 5 : TPU PAGE - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 6 : DRP DBB - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 6 : DRP DBB - #endif - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, SER_uart_irda_handler }, // 7 : UART_IRDA - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 8 : KEYBOARD - #else - { C_INTH_IRQ, C_INTH_LEVEL, 0x01, IQ_KeypadHandler }, // 8 : KEYBOARD - #endif - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 9 : DRP DBB RX - - #ifdef RVM_CAMD_SWE - - { C_INTH_IRQ, C_INTH_LEVEL, 0x03, f_camera_interrupt_manager }, // 10 : CAMERA - - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 10 : CAMERA - - #endif - - #if (PSP_STANDALONE == 0) - { C_INTH_IRQ, C_INTH_EDGE, 0x00, IQ_Gauging_Handler }, // 11 : ULPD_GAUGING - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 11 : ULPD_GAUGING - #endif - { C_INTH_IRQ, C_INTH_EDGE, 0x08, IQ_External }, // 12 : ABB_IRQ - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 13 : MSSPI - { C_INTH_IRQ, C_INTH_LEVEL, 0x06, f_dma_interrupt_manager }, // 14 : DMA - #if (PSP_STANDALONE == 0) - { C_INTH_IRQ, C_INTH_EDGE, 0x03, IQ_ApiHandler }, // 15 : API - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 15 : API - #endif - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 16 : GPIO - { C_INTH_FIQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 17 : ABB_FIQ - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 18 : DRP DBB RX - #if (PSP_STANDALONE == 0) - { C_INTH_IRQ, C_INTH_LEVEL, 0x03, IQ_GsmTim_Handler }, // 19 : ULPD GSM TIMER - #else - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 19 : ULPD GSM TIMER - #endif - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 20 : GEA - #if GSM_IDLE_RAM_DEBUG - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 21 : GPIO1 - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 22 : GPIO2 - #else - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 21 : GPIO1 - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 22 : GPIO2 - #endif - { C_INTH_FIQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 23 : CPORT - #if(OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, // 24 : USIM - #else - { C_INTH_IRQ, C_INTH_EDGE, 0x04, bspUicc_Phy_intCHandler }, // 24 : USIM - #endif - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 25 : LCD - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 26 : USB - #else - #ifdef RVM_USB_SWE - { C_INTH_IRQ, C_INTH_LEVEL, 0x03, usb_int_handler }, // 26 : USB - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, - #endif - #endif - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 27 : not used - { C_INTH_IRQ, C_INTH_LEVEL, 0x03, bspI2c_Handeler2 }, // 28 : I2C TRITON - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, f_inth_2nd_level_handler }, // 29 : 2nd Interrupt Handler - { C_INTH_IRQ, C_INTH_LEVEL, 0x03, bspI2c_Handeler1 }, // 30 : I2C - #if (OP_L1_STANDALONE == 1) - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 31 : NAND FLASH - #else - #ifdef RVM_NAN_SWE - { C_INTH_IRQ, C_INTH_LEVEL, 0x02, nan_IT_handler }, // 31 : NAND FLASH - #else - { C_INTH_IRQ, C_INTH_EDGE, 0xFF, f_inth_dummy }, - #endif - #endif - - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 0 : RNG - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 1 : SHA1/MD5 - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy }, // 2 : EMPU - { C_INTH_IRQ, C_INTH_LEVEL, 0x06, f_dma_interrupt_manager }, // 14 : DMA - { C_INTH_IRQ, C_INTH_LEVEL, 0xFF, f_inth_dummy } // 4 : Secure TIMER - }; -#endif /* CHIPSET == 15 */ - -#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END -#endif // !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) - -#if (CHIPSET == 12) - const T_DMA_TYPE_GLOBAL_PARAMETER d_dma_global_parameter= - { - #if (CHIPSET_PG == CP_PG_F751685A) - C_DMA_AUTO_GATE_ON, - #else - C_DMA_AUTO_GATE_OFF, - #endif /* endif (CHIPSET_PG == F751685A) */ - C_DMA_API_PRIO_ARM, - C_DMA_RHEA_PRIO_ARM, - C_DMA_IMIF_PRIO_CPU_4 - }; - -#endif /* (CHIPSET ==12) */ - -#if (CHIPSET == 15) - const T_DMA_TYPE_GLOBAL_PARAMETER d_dma_global_parameter= - { - C_DMA_AUTO_GATE_ON, - C_DMA_API_PRIO_ARM, - C_DMA_RHEA_PRIO_ARM, - C_DMA_IMIF_PRIO_CPU_4, - C_DMA_IPERIF_PRIO_CPU_4, // set same as the IMIF priority. Actual value need to decided - C_DMA_EMIF_DMA_PRIO_7, // Actual value need to be decided - C_DMA_EMIF_MCU_PRIO_5 // Actual value need to be decided - }; - -#endif - - -#if (GSM_IDLE_RAM != 0) - - #define IRQ_STACK_SIZE 128 - #pragma DATA_SECTION(irq_stack,".irqstk"); - UWORD32 irq_stack[IRQ_STACK_SIZE/4]; - const UWORD32 irq_stack_size = IRQ_STACK_SIZE; - - #define FIQ_STACK_SIZE 512 - #pragma DATA_SECTION(fiq_stack,".fiqstk"); - UWORD32 fiq_stack[FIQ_STACK_SIZE/4]; - const UWORD32 fiq_stack_size = FIQ_STACK_SIZE; - - #define SVC_STACK_SIZE 1024 - #pragma DATA_SECTION(svc_stack,".svcstk"); - UWORD32 svc_stack[SVC_STACK_SIZE/4]; - const UWORD32 svc_stack_size = SVC_STACK_SIZE; - - #define TIMER_HISR_STACK_SIZE 1024 - #pragma DATA_SECTION(timer_hisr_stack,".timstk"); - UWORD32 timer_hisr_stack[TIMER_HISR_STACK_SIZE/4]; - const UWORD32 timer_hisr_stack_size = TIMER_HISR_STACK_SIZE; -#endif - -/* HISR_STACK_SHARING: Create global stacks to be used by all HISRs - * having the same priority */ - - - -#if (CODE_VERSION != SIMULATION) /* * Init_Target * @@ -1599,246 +986,6 @@ } -//--> Init Added for Power Management -/******************************************************* - Configure ALL I/O pins -*******************************************************/ -void pin_configuration_all(void) -{ - pin_configuration_bluetooth(); - pin_configuration_emifs(); - pin_configuration_system(); - pin_configuration_lcd_nand(0); - pin_configuration_keypad(); - pin_configuration_sim(); - pin_configuration_radio(); - pin_configuration_usb(); - pin_configuration_camera_irda(1); -} - -/******************************************************* - Configure Bluetooth I/O pins -*******************************************************/ -void pin_configuration_bluetooth(void) -{ - GPIO_DIRECTION_OUT(37); GPIO_CLEAR_OUTPUT(37); // BT_nSHUTDOWN - CONF_GPIO_43 = MUX_CFG(1, PULLOFF); // MCSI_CK - CONF_GPIO_44 = MUX_CFG(1, PULLOFF); // MCSI_FS - CONF_GPIO_45 = MUX_CFG(1, PULLOFF); // MCSI_TX - CONF_GPIO_46 = MUX_CFG(1, PULLOFF); // MCSI_RX - CONF_UART_CTS = MUX_CFG(0, PULLOFF); // CTS - CONF_UART_RX = MUX_CFG(0, PULLOFF); // RX - CONF_UART_TX = MUX_CFG(0, PULLOFF); // TX - CONF_GPIO_37 = MUX_CFG(0, PULLOFF); // BT_SHUTDOWN -} - -/******************************************************* - Configure EMIFS I/O pins -*******************************************************/ -void pin_configuration_emifs(void) -{ - CONF_ADD_21 = MUX_CFG(0, PULLOFF); // ADD21 - CONF_GPIO_39 = MUX_CFG(1, PULLOFF); // ADD22 - CONF_GPIO_38 = MUX_CFG(0, PULLOFF); // nCS0 - CONF_NCS3 = MUX_CFG(0, PULLOFF); // nCS3 - CONF_ADV = MUX_CFG(0, PULLOFF); // ADV - CONF_NMOE = MUX_CFG(0, PULLOFF); // nMOE - CONF_RNW = MUX_CFG(0, PULLOFF); // RnW - CONF_GPIO_42 = MUX_CFG(1, PULLOFF); // CKM - CONF_NRDY = MUX_CFG(0, PULLUP); // nRDYMEM -} - -/******************************************************* - Configure system I/O pins -*******************************************************/ -void pin_configuration_system(void) -{ - GPIO_DIRECTION_IN(1); // GPIO_1 - GPIO_DIRECTION_OUT(2); GPIO_CLEAR_OUTPUT(2); // SYS_RESET - GPIO_DIRECTION_IN(10); // Not used (nEMU0) - CONF_CK13MHZ_EN = MUX_CFG(0, PULLOFF); // CK13MHZ_EN - CONF_ABB_IRQ = MUX_CFG(0, PULLUP); // ABB_IRQ - CONF_GPIO_5 = MUX_CFG(1, PULLOFF); // STARTADC - CONF_CDO = MUX_CFG(0, PULLOFF); // CDO (I2S) - CONF_CSCLK = MUX_CFG(0, PULLOFF); // CSCLK (I2S) - CONF_CSYNC = MUX_CFG(0, PULLOFF); // CSYNC (I2S) - CONF_NBSCAN = MUX_CFG(0, PULLUP); // nBSCAN - CONF_SPARE_3 = MUX_CFG(0, PULLUP); // Spare3 - CONF_TDO = MUX_CFG(0, PULLOFF); // TDO - -// JTAG pulls are disabled on I-Sample due to external buffers. -// CONF_TCK = MUX_CFG(0, PULLDOWN); // TCK -// CONF_TDI = MUX_CFG(0, PULLUP); // TDI -// CONF_TMS = MUX_CFG(0, PULLUP); // TMS -// CONF_TRST = MUX_CFG(0, PULLUP); // TRST - CONF_TCK = MUX_CFG(0, PULLOFF); // TCK - CONF_TDI = MUX_CFG(0, PULLOFF); // TDI - CONF_TMS = MUX_CFG(0, PULLOFF); // TMS - CONF_TRST = MUX_CFG(0, PULLOFF); // TRST - - CONF_VDR = MUX_CFG(0, PULLOFF); // VDR - CONF_VFSRX = MUX_CFG(0, PULLDOWN); // VFSRX - CONF_GPIO_1 = MUX_CFG(0, PULLUP); // Not used GPIO - CONF_GPIO_2 = MUX_CFG(0, PULLOFF); // SYS_RESET - CONF_GPIO_10 = MUX_CFG(1, PULLUP); // Not used (NEMU0) - CONF_GPIO_12 = MUX_CFG(2, PULLOFF); // TSPACT10 -} - -/******************************************************* - Configure LCD and NAND Flash I/O pins - Mode = 0 : LCD functional. NAND not functional - Mode = 1 : NAND functional. LCD not functional -*******************************************************/ -void pin_configuration_lcd_nand(int mode) -{ - CONF_ND_CE1 = MUX_CFG(0, PULLOFF); - CONF_GPIO_18 = MUX_CFG(1, PULLOFF); // ND_WE - CONF_GPIO_31 = MUX_CFG(1, PULLOFF); // ND_RE - CONF_GPIO_32 = MUX_CFG(1, PULLOFF); // ND_CLE - CONF_GPIO_33 = MUX_CFG(1, PULLOFF); // ND_ALE - CONF_GPIO_34 = MUX_CFG(1, PULLUP); // ND_RDY - CONF_LCD_NRST = MUX_CFG(0, PULLOFF); - CONF_LCD_RNW = MUX_CFG(0, PULLOFF); - CONF_LCD_RS = MUX_CFG(0, PULLOFF); - CONF_LCD_STB = MUX_CFG(0, PULLOFF); - CONF_GPIO_13 = MUX_CFG(1, PULLOFF); // LCD_NCS0 - switch(mode) - { - case 0: // LCD - CONF_LCD_DATA_0 = MUX_CFG(0, PULLOFF); - CONF_LCD_DATA_1 = MUX_CFG(0, PULLOFF); - CONF_LCD_DATA_2 = MUX_CFG(0, PULLOFF); - CONF_LCD_DATA_3 = MUX_CFG(0, PULLOFF); - CONF_LCD_DATA_4 = MUX_CFG(0, PULLOFF); - CONF_LCD_DATA_5 = MUX_CFG(0, PULLOFF); - CONF_LCD_DATA_6 = MUX_CFG(0, PULLOFF); - CONF_LCD_DATA_7 = MUX_CFG(0, PULLOFF); - break; - case 1: // NAND - CONF_LCD_DATA_0 = MUX_CFG(3, PULLOFF); - CONF_LCD_DATA_1 = MUX_CFG(3, PULLOFF); - CONF_LCD_DATA_2 = MUX_CFG(3, PULLOFF); - CONF_LCD_DATA_3 = MUX_CFG(3, PULLOFF); - CONF_LCD_DATA_4 = MUX_CFG(3, PULLOFF); - CONF_LCD_DATA_5 = MUX_CFG(3, PULLOFF); - CONF_LCD_DATA_6 = MUX_CFG(3, PULLOFF); - CONF_LCD_DATA_7 = MUX_CFG(3, PULLOFF); - break; - } -} - -/******************************************************* - Configure keypad pins -*******************************************************/ -void pin_configuration_keypad(void) -{ - CONF_GPIO_8 = MUX_CFG(0, PULLUP); // KBR4 - CONF_GPIO_9 = MUX_CFG(0, PULLOFF); // KBC4 - CONF_KBC_0 = MUX_CFG(0, PULLOFF); - CONF_KBC_1 = MUX_CFG(0, PULLOFF); - CONF_KBC_2 = MUX_CFG(0, PULLOFF); - CONF_KBC_3 = MUX_CFG(0, PULLOFF); - CONF_KBR_0 = MUX_CFG(0, PULLUP); - CONF_KBR_1 = MUX_CFG(0, PULLUP); - CONF_KBR_2 = MUX_CFG(0, PULLUP); - CONF_KBR_3 = MUX_CFG(0, PULLUP); -} - -/******************************************************* - Configure SIM I/O pins -*******************************************************/ -void pin_configuration_sim(void) -{ - CONF_SIM_CLK = MUX_CFG(0, PULLOFF); - CONF_SIM_IO = MUX_CFG(0, PULLOFF); - CONF_SIM_PWCTRL = MUX_CFG(0, PULLOFF); - CONF_SIM_RST = MUX_CFG(0, PULLOFF); -} - -/******************************************************* - Configure radio I/O pins -*******************************************************/ -void pin_configuration_radio(void) -{ - CONF_TSPACT_11 = MUX_CFG(0, PULLOFF); - CONF_TSPACT_12 = MUX_CFG(0, PULLOFF); - CONF_TSPACT_13 = MUX_CFG(0, PULLOFF); - CONF_TSPACT_14 = MUX_CFG(0, PULLOFF); - CONF_TSPACT_15 = MUX_CFG(0, PULLOFF); -} - -/******************************************************* - Configure USB I/O pins -*******************************************************/ -void pin_configuration_usb(void) -{ - CONF_USB_BOOT = MUX_CFG(0, PULLOFF); - CONF_USB_DAT = MUX_CFG(0, PULLDOWN); - CONF_USB_RCV = MUX_CFG(0, PULLDOWN); - //CONF_USB_SE0 = MUX_CFG(0, PULLUP); // to reduce 130 uA - CONF_USB_SE0 = MUX_CFG(0, PULLOFF); // to reduce 130 uA - CONF_USB_TXEN = MUX_CFG(0, PULLOFF); -} - -/******************************************************* - Configure Camera and IrDA I/O pins - Mode = 0 : IrDA functional. Camera not functional - Mode = 1 : Camera functional. IrDA not functional - Use mode 1 ONLY when camera is active i.e. use - mode 0 during sleep -*******************************************************/ -void pin_configuration_camera_irda(int mode) -{ - GPIO_DIRECTION_OUT(17); GPIO_SET_OUTPUT(17); // CAM_PWDN - GPIO_DIRECTION_OUT(11); GPIO_SET_OUTPUT(11); // Golden eye sleep - GPIO_DIRECTION_OUT(35); GPIO_CLEAR_OUTPUT(35); // LED_TRCH - GPIO_DIRECTION_OUT(4); GPIO_SET_OUTPUT(4); // nCAM_RST - GPIO_DIRECTION_OUT(20); GPIO_CLEAR_OUTPUT(20); // CAM_D_3 - GPIO_DIRECTION_OUT(19); GPIO_CLEAR_OUTPUT(19); // CAM_HS - GPIO_DIRECTION_OUT(21); GPIO_CLEAR_OUTPUT(21); // CAM_LCLK - GPIO_DIRECTION_OUT(36); GPIO_SET_OUTPUT(36); // IrDA_SD - CONF_GPIO_36 = MUX_CFG(0, PULLOFF); // IRDA_SD - CONF_GPIO_11 = MUX_CFG(1, PULLOFF); // Golden eye sleep (NEMU1) - CONF_GPIO_4 = MUX_CFG(0, PULLOFF); // CAM_RESET - CONF_GPIO_35 = MUX_CFG(0, PULLOFF); // LED_TORCH - CONF_GPIO_17 = MUX_CFG(0, PULLOFF); // CAM_PWDN - CONF_GPIO_23 = MUX_CFG(1, PULLDOWN); // SPI_CLK - CONF_GPIO_24 = MUX_CFG(1, PULLDOWN); // SPI_DATA_MISO - CONF_GPIO_25 = MUX_CFG(1, PULLDOWN); // SPI_DATA_MOSI - CONF_GPIO_26 = MUX_CFG(1, PULLUP); // SPI_NCS0 - CONF_GPIO_27 = MUX_CFG(1, PULLUP); // SPI_NCS1 - CONF_GPIO_22 = MUX_CFG(1, PULLOFF); // CAM_XCLK - switch(mode) - { - case 0: // IrDA or sleep - CONF_GPIO_47 = MUX_CFG(1, PULLUP); // IrDA RXIR - CONF_GPIO_0 = MUX_CFG(1, PULLOFF); // IrDA TXIR - CONF_GPIO_7 = MUX_CFG(5, PULLDOWN); // CAM_D_2 - CONF_GPIO_20 = MUX_CFG(0, PULLOFF); // CAM_D_3 = GPIO - CONF_ND_NWP = MUX_CFG(0, PULLOFF); // CAM_D_4 = ND_NWP - CONF_GPIO_30 = MUX_CFG(3, PULLDOWN); // CAM_D_5 - CONF_GPIO_29 = MUX_CFG(3, PULLDOWN); // CAM_D_6 - CONF_GPIO_28 = MUX_CFG(3, PULLUP); // CAM_D_7 - CONF_GPIO_19 = MUX_CFG(0, PULLOFF); // CAM_HS = GPIO - CONF_GPIO_21 = MUX_CFG(0, PULLOFF); // CAM_LCLK = GPIO - break; - case 1: // Camera - CONF_GPIO_47 = MUX_CFG(2, PULLOFF); // CAM_D_0 + IrDA - CONF_GPIO_0 = MUX_CFG(2, PULLOFF); // CAM_D_1 + IrDA - CONF_GPIO_7 = MUX_CFG(5, PULLOFF); // CAM_D_2 - CONF_GPIO_20 = MUX_CFG(2, PULLOFF); // CAM_D_3 - CONF_ND_NWP = MUX_CFG(2, PULLOFF); // CAM_D_4 - CONF_GPIO_30 = MUX_CFG(3, PULLOFF); // CAM_D_5 - CONF_GPIO_29 = MUX_CFG(3, PULLOFF); // CAM_D_6 - CONF_GPIO_28 = MUX_CFG(3, PULLOFF); // CAM_D_7 - CONF_GPIO_19 = MUX_CFG(1, PULLOFF); // CAM_HS - CONF_GPIO_21 = MUX_CFG(1, PULLOFF); // CAM_LCLK - break; - } -} - -//<-- Init Added for Power Management - /* * Init_Drivers * @@ -1906,81 +1053,6 @@ #endif } -#if (PSP_STANDALONE == 0) -/* - * l1_create_HISR - * - * Create L1 HISR. - */ -void l1_create_HISR (void) -{ - STATUS status; - - #if (OP_L1_STANDALONE == 0) - // Fill the entire stack with the pattern 0xFE - memset (layer_1_sync_stack, 0xFE, LAYER_1_SYNC_STACK_SIZE); - #endif - - status = NU_Create_HISR (&layer_1_sync_HISR, - "L1_HISR", - layer_1_sync_HISR_entry, - #if (OP_L1_STANDALONE == 0) - 1, - layer_1_sync_stack, - LAYER_1_SYNC_STACK_SIZE); - #else - 1, - layer_1_sync_stack, - sizeof(layer_1_sync_stack)); - #endif - - #if (L1_EXT_AUDIO_MGT) - // Create HISR for Ext MIDI activity - //================================== - status += NU_Create_HISR(&EXT_AUDIO_MGT_hisr, - "H_EXT_AUDIO_MGT", - Cust_ext_audio_mgt_hisr, - 2, - ext_audio_mgt_hisr_stack, - sizeof(ext_audio_mgt_hisr_stack)); - #endif - - #if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) ) // equivalent to an API_HISR flag - status += NU_Create_HISR(&apiHISR, - "API_HISR", - api_hisr, - 2, - API_HISR_stack, - sizeof(API_HISR_stack)); - #endif // (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) - - #if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1) // equivalent to an API_MODEM_HISR flag - // Create HISR for USF DSP interrupt !!!!. This HISR needs - // to have the highest priority since the USF status needs - // to be known before the next block starts. - //======================================================== - status += NU_Create_HISR(&api_modemHISR, - "MODEM", - api_modem_hisr, - 1, - API_MODEM_HISR_stack, - sizeof(API_MODEM_HISR_stack)); - #endif - - assert (status == 0); -} - - -void l1_create_ISR (void) -{ - l1_create_HISR(); -} -#endif - -#endif /* (CODE_VERSION != SIMULATION) */ - - - /* * Init_Unmask_IT * @@ -2190,180 +1262,3 @@ #endif /* OP_L1_STANDALONE */ } - -// From this point, everything is compiled to execute in internal RAM - -#if (((MOVE_IN_INTERNAL_RAM == 1) ^ (GSM_IDLE_RAM != 0)) && (GSM_IDLE_RAM != 0)) -#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START -#if (CODE_VERSION != SIMULATION) - - #if ((CHIPSET == 12) || (CHIPSET==15)) - - #if GSM_IDLE_RAM_DEBUG - void flash_access_handler(void) - { - l1s.gsm_idle_ram_ctl.killing_flash_access++; - } - void ext_ram_access_handler(void) - { - l1s.gsm_idle_ram_ctl.killing_ext_ram_access++; - } - #endif - - void ext_ram_irq_inth_handler(void) - { - if (!READ_TRAFFIC_CONT_STATE) - CSMI_TrafficControllerOn(); - a_inth_config[F_INTH_GET_IRQ].d_it_handler(); - } - - void ext_ram_fiq_inth_handler(void) - { - if (!READ_TRAFFIC_CONT_STATE) - CSMI_TrafficControllerOn(); - a_inth_config[F_INTH_GET_FIQ].d_it_handler(); - } - #endif -#endif // (CODE_VERSION != SIMULATION) -#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END -#endif - -#if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) -#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START - -#if (PSP_STANDALONE == 0) -/*-------------------------------------------------------*/ -/* TP_FrameIntHandler() Low Interrupt service routine */ -/*-------------------------------------------------------*/ -/* Parameters : */ -/* Return : */ -/* Functionality : activate Hisr on each frame interrupt*/ -/*-------------------------------------------------------*/ -void TP_FrameIntHandler(void) -{ - - #if (OP_L1_STANDALONE == 1) - - #if (TRACE_TYPE==1) - if (trace_info.current_config->l1_dyn_trace & 1<<L1_DYN_TRACE_L1S_CPU_LOAD) - { - TM_ResetTimer (2, 0xFFFF, 1, 0); - TM_StartTimer (2); - } - #endif - - #if (TRACE_TYPE==6) - TM_ResetTimer (2, 0xFFFF, 1, 0); - TM_StartTimer (2); - #endif - - #if (TRACE_TYPE==7) /* CPU_LOAD */ - l1_cpu_load_start(); - #endif - - #else - - #if (TRACE_TYPE == 4) && (TI_NUC_MONITOR != 1) - // TM_ResetTimer (2, TIMER_RESET_VALUE, 1, 0); - // TM_StartTimer (2); - #endif - - - #if (TI_NUC_MONITOR == 1) - /* Copy LISR buffer in Log buffer each end of HISR */ - ti_nuc_monitor_tdma_action(); - #endif - - #if WCP_PROF == 1 - prf_LogFNSwitch(l1s.actual_time.fn_mod42432); - #endif - - #endif /* OP_L1_STANDALONE */ - - NU_Activate_HISR(&layer_1_sync_HISR); /* Activate HISR interrupt */ - - #if (OP_L1_STANDALONE == 0) - #if (WCP_PROF == 1) - #if (PRF_CALIBRATION == 1) - NU_Activate_HISR(&prf_CalibrationHISR); - #endif - #endif - #endif - -} -#endif - -/* - * layer_1_sync_HISR_entry - * - * HISR associated to layer 1 sync. - */ - -void layer_1_sync_HISR_entry (void) -{ -#if (PSP_STANDALONE==0) - // Call Synchronous Layer1 - hisr(); -#endif -} -#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END -#endif // !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) - -#if (PSP_STANDALONE == 1) - -#include "nucleus.h" -#include "tc_defs.h" - -extern TC_PROTECT TCD_System_Protect; - -/*-------------------------------------------------------*/ - /* int OS_system_protect() */ - /*-------------------------------------------------------*/ - /* Parameters : none */ - /* Return : The Thread Control Block of the thread */ - /* which already owns the protection or */ - /* 0 if no protection */ - /* Functionality : Checks whether the system structures */ - /* are already protected or not */ - /*-------------------------------------------------------*/ - void OS_system_protect (void) - { - NU_Protect((NU_PROTECT*) &TCD_System_Protect); - } - - /*-------------------------------------------------------*/ - /* int OS_system_Unprotect() */ - /*-------------------------------------------------------*/ - /* Parameters : none */ - /* Return : */ - /* Functionality : unprotect the system structures */ - /*-------------------------------------------------------*/ - void OS_system_Unprotect (void) - { - NU_Unprotect(); - } - -void bspDummy_detect(void* a,int b, void* c) -{ - return; -} - -void bspDummy_remove(int a) -{ - return; -} - -void Init_Watchdog_Timer(void) -{ -/* This code is for PSP STANDALONE Build Only */ -/* WatchDog will be used by DAR enity, so using TIMER1 for OS Ticks - This will give tick period roughly equle to 4.5 ms which approx - Frame Interrupt timing */ - Dtimer1_Init_cntl(0XE9, 1, 0x07, 1); - Dtimer1_Start(1); - F_INTH_ENABLE_ONE_IT(C_INTH_TIMER1_IT); - bspUicc_drvRegister((BspUicc_CardPresentDetectHandler)bspDummy_detect, - (BspUicc_CardAbsentDetectHandler) bspDummy_remove); -} - -#endif