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annotate fpga/mcsi-rx/mcsi_rx.v @ 1:b3190839cce3

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first FPGA version, MCSI Rx only
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 11 Oct 2024 21:11:24 +0000
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b3190839cce3 first FPGA version, MCSI Rx only
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
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2 * This Verilog module captures the logic that receives 16-bit PCM samples
b3190839cce3 first FPGA version, MCSI Rx only
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3 * from MCSI. This logic block also detects loss of frame sync.
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4 */
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5
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6 module mcsi_rx (IntClk, MCSI_FS_sync, MCSI_Din_sync, MCSI_CLK_negedge,
b3190839cce3 first FPGA version, MCSI Rx only
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7 PCM_sample_out, PCM_sample_strobe, FS_lost);
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8
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9 input IntClk;
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10 input MCSI_FS_sync, MCSI_Din_sync, MCSI_CLK_negedge;
b3190839cce3 first FPGA version, MCSI Rx only
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11 output [15:0] PCM_sample_out;
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12 output PCM_sample_strobe;
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13 output FS_lost;
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14
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15 reg [15:0] shift_reg;
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16 reg [6:0] bit_count;
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17
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18 always @(posedge IntClk)
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19 if (MCSI_CLK_negedge)
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20 begin
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21 shift_reg <= {shift_reg[14:0],MCSI_Din_sync};
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22 if (MCSI_FS_sync)
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23 bit_count <= 7'd0;
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24 else if (bit_count != 7'd127)
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25 bit_count <= bit_count + 7'd1;
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26 end
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27
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28 assign PCM_sample_out = shift_reg;
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29 assign PCM_sample_strobe = MCSI_CLK_negedge && (bit_count == 7'd16);
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30 assign FS_lost = (bit_count == 7'd127);
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31
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32 endmodule