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annotate fpga/mcsi-rx/top.v @ 16:f422d19c0118 default tip

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fc-mcsi-rxtx: fix bug in PCM sample Rx
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Oct 2024 01:41:33 +0000
parents b3190839cce3
children
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1 /*
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2 * Top level Verilog module for MCSI Rx-only FPGA.
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3 */
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4
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5 module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
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6 UART_CTS, UART_DTR, UART_DSR, UART_DCD, MCSI_CLK, MCSI_FSYNCH,
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7 MCSI_TXD, MCSI_RXD);
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8
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9 input CLK12;
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10 output LED1, LED2, LED3, LED4, LED5;
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11
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12 input UART_TxD, UART_RTS, UART_DTR;
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13 output UART_RxD, UART_CTS, UART_DSR, UART_DCD;
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14
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15 input MCSI_CLK, MCSI_FSYNCH, MCSI_TXD;
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16 output MCSI_RXD;
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17
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18 /* input synchronizers */
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19
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20 wire MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync;
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21
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22 sync_inputs sync (CLK12, MCSI_CLK, MCSI_CLK_sync, MCSI_FSYNCH, MCSI_FS_sync,
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23 MCSI_TXD, MCSI_Din_sync);
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24
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25 /* running clock detector */
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26
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27 wire MCSI_CLK_running;
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28
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29 clk_check clk_check (CLK12, MCSI_CLK_sync, MCSI_CLK_running);
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30
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31 /* MCSI_CLK edge detector */
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32
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33 wire MCSI_CLK_negedge;
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34
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35 clk_edge clk_edge (CLK12, MCSI_CLK_sync, MCSI_CLK_negedge);
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36
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37 /* MCSI Rx logic */
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38
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39 wire [15:0] PCM_sample_out;
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40 wire PCM_sample_strobe;
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41 wire FS_lost, clk_fs_good;
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42
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43 mcsi_rx mcsi_rx (CLK12, MCSI_FS_sync, MCSI_Din_sync, MCSI_CLK_negedge,
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44 PCM_sample_out, PCM_sample_strobe, FS_lost);
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45
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46 assign clk_fs_good = MCSI_CLK_running && !FS_lost;
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47
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48 /* output to the host */
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49
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50 uart_tx uart_tx (CLK12, PCM_sample_strobe, PCM_sample_out, UART_RxD);
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51
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52 /* UART modem control outputs: unused */
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53
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54 assign UART_CTS = 1'b1;
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55 assign UART_DSR = 1'b0;
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56 assign UART_DCD = 1'b0;
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57
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58 /* board LEDs */
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59
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60 assign LED1 = 1'b0;
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61 assign LED2 = 1'b1;
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62 assign LED3 = 1'b0;
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63 assign LED4 = 1'b1;
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64 assign LED5 = clk_fs_good;
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65
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66 /* No MCSI output in this version */
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67
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68 assign MCSI_RXD = 1'b0;
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69
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70 endmodule