/*
 * Top level Verilog module for MCSI Rx-only FPGA.
 */

module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
	    UART_CTS, UART_DTR, UART_DSR, UART_DCD, MCSI_CLK, MCSI_FSYNCH,
	    MCSI_TXD, MCSI_RXD);

input CLK12;
output LED1, LED2, LED3, LED4, LED5;

input UART_TxD, UART_RTS, UART_DTR;
output UART_RxD, UART_CTS, UART_DSR, UART_DCD;

input MCSI_CLK, MCSI_FSYNCH, MCSI_TXD;
output MCSI_RXD;

/* input synchronizers */

wire MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync;

sync_inputs sync (CLK12, MCSI_CLK, MCSI_CLK_sync, MCSI_FSYNCH, MCSI_FS_sync,
		  MCSI_TXD, MCSI_Din_sync);

/* running clock detector */

wire MCSI_CLK_running;

clk_check clk_check (CLK12, MCSI_CLK_sync, MCSI_CLK_running);

/* MCSI_CLK edge detector */

wire MCSI_CLK_negedge;

clk_edge clk_edge (CLK12, MCSI_CLK_sync, MCSI_CLK_negedge);

/* MCSI Rx logic */

wire [15:0] PCM_sample_out;
wire PCM_sample_strobe;
wire FS_lost, clk_fs_good;

mcsi_rx mcsi_rx (CLK12, MCSI_FS_sync, MCSI_Din_sync, MCSI_CLK_negedge,
		 PCM_sample_out, PCM_sample_strobe, FS_lost);

assign clk_fs_good = MCSI_CLK_running && !FS_lost;

/* output to the host */

uart_tx uart_tx (CLK12, PCM_sample_strobe, PCM_sample_out, UART_RxD);

/* UART modem control outputs: unused */

assign UART_CTS = 1'b1;
assign UART_DSR = 1'b0;
assign UART_DCD = 1'b0;

/* board LEDs */

assign LED1 = 1'b0;
assign LED2 = 1'b1;
assign LED3 = 1'b0;
assign LED4 = 1'b1;
assign LED5 = clk_fs_good;

/* No MCSI output in this version */

assign MCSI_RXD = 1'b0;

endmodule