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comparison fpga/mcsi-rx/top.v @ 1:b3190839cce3

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first FPGA version, MCSI Rx only
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 11 Oct 2024 21:11:24 +0000
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0:4624f3da093a 1:b3190839cce3
1 /*
2 * Top level Verilog module for MCSI Rx-only FPGA.
3 */
4
5 module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
6 UART_CTS, UART_DTR, UART_DSR, UART_DCD, MCSI_CLK, MCSI_FSYNCH,
7 MCSI_TXD, MCSI_RXD);
8
9 input CLK12;
10 output LED1, LED2, LED3, LED4, LED5;
11
12 input UART_TxD, UART_RTS, UART_DTR;
13 output UART_RxD, UART_CTS, UART_DSR, UART_DCD;
14
15 input MCSI_CLK, MCSI_FSYNCH, MCSI_TXD;
16 output MCSI_RXD;
17
18 /* input synchronizers */
19
20 wire MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync;
21
22 sync_inputs sync (CLK12, MCSI_CLK, MCSI_CLK_sync, MCSI_FSYNCH, MCSI_FS_sync,
23 MCSI_TXD, MCSI_Din_sync);
24
25 /* running clock detector */
26
27 wire MCSI_CLK_running;
28
29 clk_check clk_check (CLK12, MCSI_CLK_sync, MCSI_CLK_running);
30
31 /* MCSI_CLK edge detector */
32
33 wire MCSI_CLK_negedge;
34
35 clk_edge clk_edge (CLK12, MCSI_CLK_sync, MCSI_CLK_negedge);
36
37 /* MCSI Rx logic */
38
39 wire [15:0] PCM_sample_out;
40 wire PCM_sample_strobe;
41 wire FS_lost, clk_fs_good;
42
43 mcsi_rx mcsi_rx (CLK12, MCSI_FS_sync, MCSI_Din_sync, MCSI_CLK_negedge,
44 PCM_sample_out, PCM_sample_strobe, FS_lost);
45
46 assign clk_fs_good = MCSI_CLK_running && !FS_lost;
47
48 /* output to the host */
49
50 uart_tx uart_tx (CLK12, PCM_sample_strobe, PCM_sample_out, UART_RxD);
51
52 /* UART modem control outputs: unused */
53
54 assign UART_CTS = 1'b1;
55 assign UART_DSR = 1'b0;
56 assign UART_DCD = 1'b0;
57
58 /* board LEDs */
59
60 assign LED1 = 1'b0;
61 assign LED2 = 1'b1;
62 assign LED3 = 1'b0;
63 assign LED4 = 1'b1;
64 assign LED5 = clk_fs_good;
65
66 /* No MCSI output in this version */
67
68 assign MCSI_RXD = 1'b0;
69
70 endmodule