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comparison fpga/mcsi-rx/mcsi_rx.v @ 1:b3190839cce3

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first FPGA version, MCSI Rx only
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 11 Oct 2024 21:11:24 +0000
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0:4624f3da093a 1:b3190839cce3
1 /*
2 * This Verilog module captures the logic that receives 16-bit PCM samples
3 * from MCSI. This logic block also detects loss of frame sync.
4 */
5
6 module mcsi_rx (IntClk, MCSI_FS_sync, MCSI_Din_sync, MCSI_CLK_negedge,
7 PCM_sample_out, PCM_sample_strobe, FS_lost);
8
9 input IntClk;
10 input MCSI_FS_sync, MCSI_Din_sync, MCSI_CLK_negedge;
11 output [15:0] PCM_sample_out;
12 output PCM_sample_strobe;
13 output FS_lost;
14
15 reg [15:0] shift_reg;
16 reg [6:0] bit_count;
17
18 always @(posedge IntClk)
19 if (MCSI_CLK_negedge)
20 begin
21 shift_reg <= {shift_reg[14:0],MCSI_Din_sync};
22 if (MCSI_FS_sync)
23 bit_count <= 7'd0;
24 else if (bit_count != 7'd127)
25 bit_count <= bit_count + 7'd1;
26 end
27
28 assign PCM_sample_out = shift_reg;
29 assign PCM_sample_strobe = MCSI_CLK_negedge && (bit_count == 7'd16);
30 assign FS_lost = (bit_count == 7'd127);
31
32 endmodule