FreeCalypso > hg > fc-pcm-if
diff fpga/tools/yosys-tee @ 0:4624f3da093a
starting project with FPGA infra from fc-sim-sniff
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Fri, 11 Oct 2024 18:36:25 +0000 |
parents | |
children |
line wrap: on
line diff
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fpga/tools/yosys-tee Fri Oct 11 18:36:25 2024 +0000 @@ -0,0 +1,27 @@ +#!/bin/sh + +if [ $# -lt 4 ] +then + echo "usage: $0 top-module json-output report-out verilog-src..." 1>&2 + exit 1 +fi + +top="$1" +json="$2" +report="$3" + +shift +shift +shift + +rm -f "$json" +yosys -p "synth_ice40 -top $top -json $json" "$@" | tee "$report" + +if [ -f "$json" ] +then + echo "$json created, declaring success" + exit 0 +else + echo "$json NOT created, declaring error" + exit 1 +fi