--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/common/icestick-mcsi.pcf	Fri Oct 11 18:36:25 2024 +0000
@@ -0,0 +1,28 @@
+# Pin Constraint File for the HK1X FPGA as wired on the Icestick board,
+# adapted for FCDEV3B MCSI application.
+
+# Board essentials
+set_io	CLK12		21
+set_io	LED1		99
+set_io	LED2		98
+set_io	LED3		97
+set_io	LED4		96
+set_io	LED5		95
+
+# FT2232H UART channel, signal names are from FT2232H DTE perspective,
+# the logic in the FPGA has to act as DCE.
+
+set_io	UART_TxD	9
+set_io	UART_RxD	8
+set_io	UART_RTS	7
+set_io	UART_CTS	4
+set_io	UART_DTR	3
+set_io	UART_DSR	2
+set_io	UART_DCD	1
+
+# Calypso MCSI connection on J1 header pins, pinout chosen to match FCDEV3B.
+
+set_io	MCSI_CLK	115
+set_io	MCSI_RXD	114
+set_io	MCSI_TXD	113
+set_io	MCSI_FSYNCH	112

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/tools/yosys-tee	Fri Oct 11 18:36:25 2024 +0000
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+if [ $# -lt 4 ]
+then
+	echo "usage: $0 top-module json-output report-out verilog-src..." 1>&2
+	exit 1
+fi
+
+top="$1"
+json="$2"
+report="$3"
+
+shift
+shift
+shift
+
+rm -f "$json"
+yosys -p "synth_ice40 -top $top -json $json" "$@" | tee "$report"
+
+if [ -f "$json" ]
+then
+	echo "$json created, declaring success"
+	exit 0
+else
+	echo "$json NOT created, declaring error"
+	exit 1
+fi

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/tools/yosys-wrap	Fri Oct 11 18:36:25 2024 +0000
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+if [ $# -lt 3 ]
+then
+	echo "usage: $0 top-module json-output verilog-src..." 1>&2
+	exit 1
+fi
+
+top="$1"
+json="$2"
+
+shift
+shift
+
+rm -f "$json"
+yosys -p "synth_ice40 -top $top -json $json" "$@"
+
+if [ -f "$json" ]
+then
+	echo "$json created, declaring success"
+	exit 0
+else
+	echo "$json NOT created, declaring error"
+	exit 1
+fi