FreeCalypso > hg > fc-pcm-if

diff fpga/tools/yosys-wrap @ 0:4624f3da093a

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starting project with FPGA infra from fc-sim-sniff
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 11 Oct 2024 18:36:25 +0000
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/tools/yosys-wrap	Fri Oct 11 18:36:25 2024 +0000
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+if [ $# -lt 3 ]
+then
+	echo "usage: $0 top-module json-output verilog-src..." 1>&2
+	exit 1
+fi
+
+top="$1"
+json="$2"
+
+shift
+shift
+
+rm -f "$json"
+yosys -p "synth_ice40 -top $top -json $json" "$@"
+
+if [ -f "$json" ]
+then
+	echo "$json created, declaring success"
+	exit 0
+else
+	echo "$json NOT created, declaring error"
+	exit 1
+fi