FreeCalypso > hg > fc-selenite

annotate src/cs/system/main/gcc/bootentry.S @ 165:2c82c413775f

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gcc bootentry.S: SE J100 target support
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 06 Apr 2019 08:49:03 +0000
parents 2de9e5f46550
children 7409b22cac61
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
89
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * This assembly module is our counterpart to TI's int.s: all boot entry
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 * point code that needs to be at the beginning of the flash resides here.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 #include "asm_defs.h"
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 #include "fc-target.cfg"
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 #if defined(FLASH) && !defined(CONFIG_TARGET_COMPAL)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 /*
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 * Put something sensible in the boot ROM overlay area, just for the
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 * heck of it, or for extra robustness.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 .section bootrom.overlay,"ax",%progbits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 .code 32
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 .org 0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 b BootROM_disabled_entry
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 #include "vectors.S"
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 BootROM_disabled_entry:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 /* copy the boot ROM switch code to IRAM and jump to it */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 ldr r4, =__romswitch_flash_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 ldr r5, =__romswitch_ram_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 ldr r2, =__romswitch_size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 1: ldr r0, [r4], #4
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 str r0, [r5], #4
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 subs r2, r2, #4
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 bhi 1b
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28 ldr pc, =__romswitch_ram_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30 .section bootrom.switch,"ax",%progbits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31 .code 32
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 .org 0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33 @ enable the Calypso boot ROM
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34 ldr r1, =0xFFFFFB10
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35 mov r2, #0x0100
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
36 strh r2, [r1]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37 @ jump to it!
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
38 mov pc, #0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39 #endif
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
40
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
41 .section .inttext,"ax",%progbits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
42 .code 32
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
44 #ifdef FLASH
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45 .org 0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
46 #ifndef CONFIG_TARGET_COMPAL
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
47 /* sane targets with Calypso boot ROM enabled by the PCB wiring */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
48 /* provide the necessary magic words for the boot ROM */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
49 .word 0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50 .word _Firmware_boot_entry
165
2c82c413775f gcc bootentry.S: SE J100 target support
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
51 #elif defined(CONFIG_TARGET_C11X) || defined(CONFIG_TARGET_C139) || \
2c82c413775f gcc bootentry.S: SE J100 target support
Mychaela Falconia <falcon@freecalypso.org>
parents: 90
diff changeset
52 defined(CONFIG_TARGET_J100)
89
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
53 /*
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
54 * On this target we'll put a patched version of Compal's boot code in
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
55 * flash sector 0 (the brickable one); the main fw images will then be
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
56 * flashed starting at 0x10000, which is where our modified boot code
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
57 * expects them to be. The interface between our hacked boot code and
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
58 * the main fw has been made to mimic TI's TCS211 reference fw.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
59 */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
60 #include "vectors.S"
90
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
61 .org 0x58 /* entry point at 0x10058 */
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
62 b _Firmware_boot_entry
89
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
63 #elif defined(CONFIG_TARGET_C155)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
64 /*
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
65 * On this target the hand-off point between the bootloader and the main
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
66 * fw image coincides with a flash erase block boundary, thus we can reuse
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
67 * the original bootloader without having to reflash the brickable sector
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
68 * at all. The following bits will appear at 0x20000.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
69 */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
70 .asciz "FreeCalypso firmware for C155/156 target"
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
71 .org 0xE0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
72 /* C155/156 bootloader jumps here */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
73 b _Firmware_boot_entry
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
74 #include "vectors.S"
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
75 #else
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
76 #error "Unsupported flash boot configuration"
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
77 #endif
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
78 #endif
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
79
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
80 /* definitions from TI's int.s */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
81
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
82 #define IRQ_STACK_SIZE 128
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
83 #define FIQ_STACK_SIZE 512
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
84 #define SYSTEM_SIZE 1024
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
85 #define TIMER_SIZE 1024
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
86 #define TIMER_PRIORITY 2
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
87
90
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
88 @ TI's literal pool before the entry point
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
89
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
90 addrCS0: .word 0xfffffb00 @ CS0 address space
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
91
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
92 EX_MPU_CONF_REG: .word 0xFFFEF006 @ Extended MPU configuration register address
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
93 EX_FLASH_VALUE: .short 0x0008 @ set bit to enable A22
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
94
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
95 .balign 4
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
96
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
97 CNTL_ARM_CLK_REG: .word 0xFFFFFD00 @ CNTL_ARM_CLK register address
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
98 DPLL_CNTRL_REG: .word 0xFFFF9800 @ DPLL control register address
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
99 EXTRA_CONTROL_REG: .word 0xFFFFFB10 @ Extra Control register CONF address
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
100 MPU_CTL_REG: .word 0xFFFFFF08 @ MPU_CTL register address
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
101
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
102 CNTL_ARM_CLK_RST: .short 0x1081 @ Initialization of CNTL_ARM_CLK register
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
103 @ Use DPLL, Divide by 1
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
104 DPLL_CONTROL_RST: .short 0x2002 @ Configure DPLL in default state
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
105 DISABLE_DU_MASK: .short 0x0800 @ Mask to Disable the DU module
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
106 ENABLE_DU_MASK: .short 0xF7FF @ Mask to Enable the DU module
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
107 MPU_CTL_RST: .short 0x0000 @ Reset value of MPU_CTL register - All protections disabled
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
108
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
109 CS0_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
110 CS1_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
111 CS2_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
112 CS3_MEM_REG: .short 0x283 @ 1 Dummy Cycle 8 bit 3 WS SW BP enable
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
113 CS4_MEM_REG: .short 0xe85 @ default reset value
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
114 CS6_MEM_REG: .short 0x2c0 @ Internal RAM init : 0 WS, 32 bits, little, write enable
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
115 CS7_MEM_REG: .short 0x040 @ Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
116 CTL_MEM_REG: .short 0x02a @ rhea strobe 0/1 + API access size adaptation
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
117
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
118 .balign 4
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
119
89
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120 .globl _Firmware_boot_entry
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121 _Firmware_boot_entry:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 @ TI's code from int.s follows
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 @ Configure DPLL register with reset value
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 ldr r1,DPLL_CNTRL_REG @ Load address of DPLL register in R1
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 ldrh r2,DPLL_CONTROL_RST @ Load DPLL reset value in R2
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 strh r2,[r1] @ Store DPLL reset value in DPLL register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 @ Wait that DPLL goes in BYPASS mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 Wait_DPLL_Bypass:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 ldr r2,[r1] @ Load DPLL register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 and r2,r2,#1 @ Perform a mask on bit 0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 cmp r2,#1 @ Compare DPLL lock bit
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 beq Wait_DPLL_Bypass @ Wait Bypass mode (i.e. bit[0]='0')
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 @ Configure CNTL_ARM_CLK register with reset value: DPLL is used to
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 @ generate ARM clock with division factor of 1.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 ldr r1,CNTL_ARM_CLK_REG @ Load address of CNTL_ARM_CLK register in R1
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 ldrh r2,CNTL_ARM_CLK_RST @ Load CNTL_ARM_CLK reset value in R2
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 strh r2,[r1] @ Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 @ Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 ldr r1,EXTRA_CONTROL_REG @ Load address of Extra Control register CONF
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 ldrh r2,ENABLE_DU_MASK @ Load mask to write in Extra Control register CONF
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 ldrh r0,[r1] @ Load Extra Control register CONF in r0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 and r0,r0,r2 @ Enable DU module
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 strh r0,[r1] @ Store configuration in Extra Control register CONF
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 @ Disable all MPU protections
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 ldr r1,MPU_CTL_REG @ Load address of MPU_CTL register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 ldrh r2,MPU_CTL_RST @ Load reset value of MPU_CTL register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 strh r2,[r1] @ Store reset value of MPU_CTL register
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 @ MEMIF timing setup
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 ldr r1,addrCS0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 ldrh r2,CS0_MEM_REG @ ROM initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 strh r2,[r1] @ CS0
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 ldrh r2,CS1_MEM_REG @ RAM Initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 strh r2,[r1,#2] @ CS1
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 ldrh r2,CS2_MEM_REG @ RAM Initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 strh r2,[r1,#4] @ CS2
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 ldrh r2,CS3_MEM_REG @ Parallel I/O on B-Sample
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 strh r2,[r1,#6] @ CS3 (unused on EVA4?)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 ldrh r2,CS4_MEM_REG @ Latch on B-Sample
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 strh r2,[r1,#0xa] @ CS4 (unused on EVA4)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 ldrh r2,CS6_MEM_REG @ Internal SRAM initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 strh r2,[r1,#0xc] @ CS6 Internal RAM
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 ldrh r2,CS7_MEM_REG @ Internal SRAM initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 strh r2,[r1,#0x8] @ CS7 Internal Boot ROM
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 ldrh r2,CTL_MEM_REG @ API-RHEA configuration
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 strh r2,[r1,#0xe]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 @ enable ADD22
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 ldr r1,EX_MPU_CONF_REG
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 ldrh r2,[r1]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 ldr r0,EX_FLASH_VALUE
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 orr r0, r0, r2
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 strh r0,[r1]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 /* Ensure that the processor is in supervisor mode. */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 BIC a1,a1,#MODE_MASK @ Clear the mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 ORR a1,a1,#SUP_MODE @ Set the supervisor mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 ORR a1,a1,#LOCKOUT @ Ensure IRQ and FIQ interrupts are
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 @ locked out
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206 MSR CPSR,a1 @ Setup the new CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 /*
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 * FreeCalypso Selenite: if this is a flash build,
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 * copy IRAM code and .data from flash to RAM.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 #ifdef FLASH
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 /* copy iram.text to where it's supposed to be */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 ldr r8, =__iramtext_flash_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 ldr r9, =__iramtext_ram_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 ldr r10, =__iramtext_size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 1: ldmia r8!, {r0-r7}
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 stmia r9!, {r0-r7}
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 subs r10, r10, #0x20
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 bhi 1b
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 /* likewise copy .data from flash to XRAM */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 ldr r8, =__initdata_flash_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 ldr r9, =__initdata_ram_addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 ldr r10, =__initdata_size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 1: ldmia r8!, {r0-r7}
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 stmia r9!, {r0-r7}
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 subs r10, r10, #0x20
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 bhi 1b
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 #endif
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 /* Both flash and XRAM builds: zero .bss */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 ldr r0, =__intbss_start
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 ldr r1, =__intbss_size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 bl bzero
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 ldr r0, =__extbss_start
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 ldr r1, =__extbss_size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 bl bzero
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 @ TI's int.s code continues
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 @ Initialize the system stack pointers. This is done after the BSS is
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 @ cleared because the TCD_System_Stack pointer is a BSS variable! It is
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 @ assumed that the .cmd file is written to direct where these stacks should
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 @ be allocated and to align them on double word boundaries.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 LDR a1,StackSegment @ Pickup the begining address from .cmd file
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 @ (is aligned on 8 byte boundary)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 MOV a2,#SYSTEM_SIZE @ Pickup system stack size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 SUB a2,a2,#4 @ Subtract one word for first addr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 ADD a3,a1,a2 @ Build start of system stack area
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 MOV v7,a1 @ Setup initial stack limit
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 LDR a4,System_Limit @ Pickup system stack limit address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 STR v7,[a4, #0] @ Save stack limit
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 MOV sp,a3 @ Setup initial stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 LDR a4,System_Stack @ Pickup system stack address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 STR sp,[a4, #0] @ Save stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 MOV a2,#IRQ_STACK_SIZE @ Pickup IRQ stack size in bytes
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 ADD a3,a3,a2 @ Allocate IRQ stack area
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 BIC a1,a1,#MODE_MASK @ Clear the mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 ORR a1,a1,#IRQ_MODE @ Set the IRQ mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 MSR CPSR,a1 @ Move to IRQ mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 MOV sp,a3 @ Setup IRQ stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 MOV a2,#FIQ_STACK_SIZE @ Pickup FIQ stack size in bytes
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 ADD a3,a3,a2 @ Allocate FIQ stack area
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 BIC a1,a1,#MODE_MASK @ Clear the mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 ORR a1,a1,#FIQ_MODE @ Set the FIQ mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 MSR CPSR,a1 @ Move to the FIQ mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 MOV sp,a3 @ Setup FIQ stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 BIC a1,a1,#MODE_MASK @ Clear the mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 ORR a1,a1,#ABORT_MODE @ Set the Abort mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 MSR CPSR,a1 @ Move to the Abort mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279 LDR sp,Exception_Stack @ Setup Abort stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 BIC a1,a1,#MODE_MASK @ Clear the mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 ORR a1,a1,#UNDEF_MODE @ Set the Undefined mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 MSR CPSR,a1 @ Move to the Undefined mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 LDR sp,Exception_Stack @ Setup Undefined stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 @ (should never be used)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 @ go to Supervisor Mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 MRS a1,CPSR @ Pickup current CPSR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 BIC a1,a1,#MODE_MASK @ Clear mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 ORR a1,a1,#SUP_MODE @ Set the supervisor mode bits
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 MSR CPSR,a1 @ All interrupt stacks are setup,
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 @ return to supervisor mode
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 @ /* Define the global data structures that need to be initialized by this
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 @ routine. These structures are used to define the system timer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 @ management HISR. */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 @ TMD_HISR_Stack_Ptr = (VOID *) a3;
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 @ TMD_HISR_Stack_Size = TIMER_SIZE;
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 @ TMD_HISR_Priority = TIMER_PRIORITY;
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 @ TMD_HISR_Stack_Ptr points at the top (the lowest address) of the allocated
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303 @ area. The Timer HISR (called "SYSTEM H") and its related stack will be created
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 @ in TMI_Initialize(). The current stack pointer will be set at the bottom (the
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 @ lowest address) of the expected area.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 LDR a4,HISR_Stack_Ptr @ Pickup variable's address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308 ADD a3,a3,#4 @ Increment to next available word
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 STR a3,[a4, #0] @ Setup timer HISR stack pointer
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 MOV a2,#TIMER_SIZE @ Pickup the timer HISR stack size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311 BIC a2,a2,#3 @ Insure word alignment
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 ADD a3,a3,a2 @ Allocate the timer HISR stack
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 @ from available memory
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 LDR a4,HISR_Stack_Size @ Pickup variable's address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 STR a2,[a4, #0] @ Setup timer HISR stack size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 MOV a2,#TIMER_PRIORITY @ Pickup timer HISR priority (0-2)
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 LDR a4,HISR_Priority @ Pickup variable's address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 STR a2,[a4, #0] @ Setup timer HISR priority
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 /* TI's original code called f_load_int_mem() at this point */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 /* let's do our internal ROM enable step here */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 ldr r1, EXTRA_CONTROL_REG
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 ldrh r0, [r1, #0]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325 bic r0, #0x0300
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 orr r0, #0x0100
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327 strh r0, [r1, #0]
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 @ We now fill up the System, IRQ, FIQ and System Timer HISR stacks with 0xFE for
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 @ checking the status of the stacks later.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 @ inputs:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 @ a3 still has the bottom of all four stacks and is aligned.
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 @ algorithm:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 @ We start from the top of all four stacks (*System_Limit), which is
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 @ necessarily aligned. We store 0xFEFEFEFE until we have filled the
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 @ bottom of the fourth stack
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 @ outputs:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 @ memory has 0xFE on all four stacks: System, FIQ, IRQ and System Timer HISR
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339 @ a3 still has the bottom of all four stacks
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 LDR a2,System_Limit @ pickup system stack limit address
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 LDR a1,[a2] @ a1 = StackSegment
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 LDR a4,=0xFEFEFEFE
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 fill_stack:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 STR a4,[a1],#4 @ store a word and increment by four
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 CMP a1,a3 @ is this the last address?
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 BLT fill_stack @ if not, loop back
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 @ /* Call INC_Initialize with a pointer to the first available memory
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 @ address after the compiler's global data. This memory may be used
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 @ by the application. */
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 @ INC_Initialize(first_available_memory);
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 @
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 MOV a1,a3 @ Pass the first available memory
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 B INC_Initialize @ to high-level initialization
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358
90
2de9e5f46550 .../main/gcc/bootentry.S: the literal pool needs to be arranged
Mychaela Falconia <falcon@freecalypso.org>
parents: 89
diff changeset
359 @ literal pool from int.s (after the code)
89
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 StackSegment:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 .word _Stack_segment_start
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364 System_Limit:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 .word TCT_System_Limit
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 System_Stack:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368 .word TCD_System_Stack
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 HISR_Stack_Ptr:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371 .word TMD_HISR_Stack_Ptr
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 HISR_Stack_Size:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 .word TMD_HISR_Stack_Size
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 HISR_Priority:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 .word TMD_HISR_Priority
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 Exception_Stack:
b398f288d20a src/cs/system/main/gcc/bootentry.S: written
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 .word _Except_Stack_SP