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changeset 90:2de9e5f46550

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.../main/gcc/bootentry.S: the literal pool needs to be arranged the way TI had it
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 20 Jul 2018 23:39:27 +0000
parents b398f288d20a
children 081dd22ca6a2
files src/cs/system/main/gcc/bootentry.S
diffstat 1 files changed, 35 insertions(+), 28 deletions(-) [+]
line wrap: on
line diff
--- a/src/cs/system/main/gcc/bootentry.S	Fri Jul 20 23:14:00 2018 +0000
+++ b/src/cs/system/main/gcc/bootentry.S	Fri Jul 20 23:39:27 2018 +0000
@@ -57,7 +57,8 @@
  * the main fw has been made to mimic TI's TCS211 reference fw.
  */
 #include "vectors.S"
-	.org	0x58	/* put _Firmware_boot_entry at 0x10058 */
+	.org	0x58	/* entry point at 0x10058 */
+	b	_Firmware_boot_entry
 #elif defined(CONFIG_TARGET_C155)
 /*
  * On this target the hand-off point between the bootloader and the main
@@ -83,6 +84,38 @@
 #define	TIMER_SIZE	1024
 #define	TIMER_PRIORITY	2
 
+@ TI's literal pool before the entry point
+
+addrCS0:           .word   0xfffffb00	@ CS0 address space
+
+EX_MPU_CONF_REG:   .word   0xFFFEF006   @ Extended MPU configuration register address
+EX_FLASH_VALUE:    .short  0x0008       @ set bit to enable A22
+
+		   .balign 4
+
+CNTL_ARM_CLK_REG:  .word   0xFFFFFD00   @ CNTL_ARM_CLK register address
+DPLL_CNTRL_REG:    .word   0xFFFF9800   @ DPLL control register address
+EXTRA_CONTROL_REG: .word   0xFFFFFB10   @ Extra Control register CONF address
+MPU_CTL_REG:       .word   0xFFFFFF08   @ MPU_CTL register address
+
+CNTL_ARM_CLK_RST:  .short  0x1081       @ Initialization of CNTL_ARM_CLK register
+                                        @ Use DPLL, Divide by 1
+DPLL_CONTROL_RST:  .short  0x2002       @ Configure DPLL in default state
+DISABLE_DU_MASK:   .short  0x0800       @ Mask to Disable the DU module
+ENABLE_DU_MASK:    .short  0xF7FF       @ Mask to Enable the DU module
+MPU_CTL_RST:       .short  0x0000       @ Reset value of MPU_CTL register - All protections disabled
+
+CS0_MEM_REG:   .short  0x2a1  @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
+CS1_MEM_REG:   .short  0x2a1  @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
+CS2_MEM_REG:   .short  0x2a1  @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
+CS3_MEM_REG:   .short  0x283  @ 1 Dummy Cycle  8 bit 3 WS SW BP enable
+CS4_MEM_REG:   .short  0xe85  @ default reset value
+CS6_MEM_REG:   .short  0x2c0  @ Internal RAM   init : 0 WS, 32 bits, little, write enable
+CS7_MEM_REG:   .short  0x040  @ Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
+CTL_MEM_REG:   .short  0x02a  @ rhea strobe 0/1 + API access size adaptation
+
+		.balign	4
+
 	.globl	_Firmware_boot_entry
 _Firmware_boot_entry:
 @  TI's code from int.s follows
@@ -322,33 +355,7 @@
 	MOV     a1,a3                       @ Pass the first available memory
 	B       INC_Initialize              @ to high-level initialization
 
-@ literal pool from int.s
-
-addrCS0:           .word   0xfffffb00	@ CS0 address space
-
-EX_MPU_CONF_REG:   .word   0xFFFEF006   @ Extended MPU configuration register address
-EX_FLASH_VALUE:    .short  0x0008       @ set bit to enable A22
-
-CNTL_ARM_CLK_REG:  .word   0xFFFFFD00   @ CNTL_ARM_CLK register address
-DPLL_CNTRL_REG:    .word   0xFFFF9800   @ DPLL control register address
-EXTRA_CONTROL_REG: .word   0xFFFFFB10   @ Extra Control register CONF address
-MPU_CTL_REG:       .word   0xFFFFFF08   @ MPU_CTL register address
-
-CNTL_ARM_CLK_RST:  .short  0x1081       @ Initialization of CNTL_ARM_CLK register
-                                        @ Use DPLL, Divide by 1
-DPLL_CONTROL_RST:  .short  0x2002       @ Configure DPLL in default state
-DISABLE_DU_MASK:   .short  0x0800       @ Mask to Disable the DU module
-ENABLE_DU_MASK:    .short  0xF7FF       @ Mask to Enable the DU module
-MPU_CTL_RST:       .short  0x0000       @ Reset value of MPU_CTL register - All protections disabled
-
-CS0_MEM_REG:   .short  0x2a1  @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
-CS1_MEM_REG:   .short  0x2a1  @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
-CS2_MEM_REG:   .short  0x2a1  @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
-CS3_MEM_REG:   .short  0x283  @ 1 Dummy Cycle  8 bit 3 WS SW BP enable
-CS4_MEM_REG:   .short  0xe85  @ default reset value
-CS6_MEM_REG:   .short  0x2c0  @ Internal RAM   init : 0 WS, 32 bits, little, write enable
-CS7_MEM_REG:   .short  0x040  @ Internal BOOT ROM   init : 0 WS, 32 bits, little, write disable
-CTL_MEM_REG:   .short  0x02a  @ rhea strobe 0/1 + API access size adaptation
+@ literal pool from int.s (after the code)
 
 StackSegment:
 	.word	_Stack_segment_start