FreeCalypso > hg > fc-selenite

comparison src/cs/drivers/drv_app/uart/uartfax.c @ 203:ba3693cbd40e

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src/cs: sync with Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 29 Jun 2020 00:27:13 +0000
parents 7409b22cac61
children d0547d47260a
comparison
equal deleted inserted replaced
202:ae3106eb5923 203:ba3693cbd40e
114 114
115 #include "memif/mem.h" 115 #include "memif/mem.h"
116 116
117 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) 117 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41))
118 #include "armio/armio.h" 118 #include "armio/armio.h"
119 #endif
120
121 #ifdef CONFIG_TANGO_MODEM
122 extern SYS_UWORD8 AI_Tango_pinmux[4];
119 #endif 123 #endif
120 124
121 /* 125 /*
122 * Maximal value for an unsigned 32 bits. 126 * Maximal value for an unsigned 32 bits.
123 */ 127 */
2594 else { 2598 else {
2595 2599
2596 uart->tx_stopped_by_driver = 0; 2600 uart->tx_stopped_by_driver = 0;
2597 #ifdef CONFIG_TARGET_GTAMODEM 2601 #ifdef CONFIG_TARGET_GTAMODEM
2598 AI_ResetBit(1); 2602 AI_ResetBit(1);
2603 #elif defined(CONFIG_TANGO_MODEM)
2604 if (AI_Tango_pinmux[0] == 0x82)
2605 AI_ResetBit(1);
2599 #endif 2606 #endif
2600 2607
2601 #if ((CHIPSET != 5) && (CHIPSET != 6)) 2608 #if ((CHIPSET != 5) && (CHIPSET != 6))
2602 /* 2609 /*
2603 * Disable sleep mode. 2610 * Disable sleep mode.
3019 /* 3026 /*
3020 * Select I/O for DCD and configure it as output. 3027 * Select I/O for DCD and configure it as output.
3021 * DCD should start HIGH (not asserted). 3028 * DCD should start HIGH (not asserted).
3022 */ 3029 */
3023 3030
3031 #ifdef CONFIG_TANGO_MODEM
3032 if (AI_Tango_pinmux[1] & 0x08) {
3033 #endif
3024 *((volatile SYS_UWORD16 *) EXTENDED_MCU_REG) &= ~(1 << IO_DCD); 3034 *((volatile SYS_UWORD16 *) EXTENDED_MCU_REG) &= ~(1 << IO_DCD);
3025 AI_ConfigBitAsOutput (ARMIO_DCD); 3035 AI_ConfigBitAsOutput (ARMIO_DCD);
3026 AI_SetBit (ARMIO_DCD); 3036 AI_SetBit (ARMIO_DCD);
3037 #ifdef CONFIG_TANGO_MODEM
3038 }
3039 #endif
3027 3040
3028 /* 3041 /*
3029 * Select I/O for DTR and configure it as input. 3042 * Select I/O for DTR and configure it as input.
3030 * An interrupt is used to detect a change of state of DTR. Falling edge 3043 * An interrupt is used to detect a change of state of DTR. Falling edge
3031 * or rising edge is selected according to the state of DTR. 3044 * or rising edge is selected according to the state of DTR.
3032 */ 3045 */
3033 3046
3047 #ifdef CONFIG_TANGO_MODEM
3048 if (AI_Tango_pinmux[1] & 0x80) {
3049 #endif
3034 *((volatile SYS_UWORD16 *) ASIC_CONFIG_REG) &= ~(1 << IO_DTR); 3050 *((volatile SYS_UWORD16 *) ASIC_CONFIG_REG) &= ~(1 << IO_DTR);
3035 AI_ConfigBitAsInput (ARMIO_DTR); 3051 AI_ConfigBitAsInput (ARMIO_DTR);
3036 uart->dtr_level = AI_ReadBit (ARMIO_DTR); 3052 uart->dtr_level = AI_ReadBit (ARMIO_DTR);
3037 3053
3038 if (uart->dtr_level) 3054 if (uart->dtr_level)
3039 AI_SelectIOForIT (ARMIO_DTR, ARMIO_FALLING_EDGE); 3055 AI_SelectIOForIT (ARMIO_DTR, ARMIO_FALLING_EDGE);
3040 else 3056 else
3041 AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE); 3057 AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE);
3042 3058
3043 AI_UnmaskIT (ARMIO_MASKIT_GPIO); 3059 AI_UnmaskIT (ARMIO_MASKIT_GPIO);
3060 #ifdef CONFIG_TANGO_MODEM
3061 } else
3062 uart->dtr_level = 0;
3063 #endif
3044 3064
3045 /* 3065 /*
3046 * Reset the 2 indexes of the circular buffer of 2 elements. 3066 * Reset the 2 indexes of the circular buffer of 2 elements.
3047 * The circular buffer does not need to be initialized. 3067 * The circular buffer does not need to be initialized.
3048 */ 3068 */
3221 * Mask all interrupts causes and disable sleep mode and low power mode. 3241 * Mask all interrupts causes and disable sleep mode and low power mode.
3222 */ 3242 */
3223 3243
3224 WRITE_UART_REGISTER (uart, IER, 0x00); 3244 WRITE_UART_REGISTER (uart, IER, 0x00);
3225 3245
3226 #if UARTFAX_CLASSIC_DTR_DCD 3246 #ifdef CONFIG_TANGO_MODEM
3247 if (AI_Tango_pinmux[1] & 0x80)
3248 AI_MaskIT (ARMIO_MASKIT_GPIO);
3249 #elif UARTFAX_CLASSIC_DTR_DCD
3227 AI_MaskIT (ARMIO_MASKIT_GPIO); 3250 AI_MaskIT (ARMIO_MASKIT_GPIO);
3228 #elif (CHIPSET == 12) 3251 #elif (CHIPSET == 12)
3229 DISABLE_DSR_INTERRUPT (uart); 3252 DISABLE_DSR_INTERRUPT (uart);
3230 #endif 3253 #endif
3231 3254
3367 #if UARTFAX_CLASSIC_DTR_DCD 3390 #if UARTFAX_CLASSIC_DTR_DCD
3368 /* 3391 /*
3369 * Read the state of DTR and select the edge. 3392 * Read the state of DTR and select the edge.
3370 */ 3393 */
3371 3394
3395 #ifdef CONFIG_TANGO_MODEM
3396 if (AI_Tango_pinmux[1] & 0x80) {
3397 #endif
3372 uart->dtr_level = AI_ReadBit (ARMIO_DTR); 3398 uart->dtr_level = AI_ReadBit (ARMIO_DTR);
3373 3399
3374 if (uart->dtr_level) 3400 if (uart->dtr_level)
3375 AI_SelectIOForIT (ARMIO_DTR, ARMIO_FALLING_EDGE); 3401 AI_SelectIOForIT (ARMIO_DTR, ARMIO_FALLING_EDGE);
3376 else 3402 else
3377 AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE); 3403 AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE);
3378 3404
3379 AI_UnmaskIT (ARMIO_MASKIT_GPIO); 3405 AI_UnmaskIT (ARMIO_MASKIT_GPIO);
3406 #ifdef CONFIG_TANGO_MODEM
3407 } else
3408 uart->dtr_level = 0;
3409 #endif
3410
3380 #elif (CHIPSET == 12) 3411 #elif (CHIPSET == 12)
3381 /* 3412 /*
3382 * Read the state of DTR - No need to reload MSR register since its value 3413 * Read the state of DTR - No need to reload MSR register since its value
3383 * is still stored in the "status" local variable. 3414 * is still stored in the "status" local variable.
3384 */ 3415 */
3593 /* 3624 /*
3594 WRITE_UART_REGISTER ( 3625 WRITE_UART_REGISTER (
3595 uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP); 3626 uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP);
3596 */ 3627 */
3597 #endif 3628 #endif
3598 3629
3630 /*
3631 * Openmoko made the change of enabling hardware assisted CTS
3632 * flow control in the UART when RTS/CTS flow control is used -
3633 * it is a change which we have retained in FreeCalypso -
3634 * but they forgot to turn this hw mode off if RTS/CTS flow control
3635 * is deselected at the application level. We (FreeCalypso)
3636 * are now fixing the latter defect ourselves.
3637 */
3599 if (fcMode == fc_rts) { 3638 if (fcMode == fc_rts) {
3600 #if 1 // Dmitriy: enable hardware assisted CTS 3639 /* begin Openmoko change */
3601 volatile SYS_UWORD8 oldValue; 3640 SYS_UWORD8 oldValue;
3602 3641
3603 oldValue = READ_UART_REGISTER (uart, LCR); 3642 oldValue = READ_UART_REGISTER (uart, LCR);
3604 3643
3605 // LCR value to allow acces to EFR 3644 // LCR value to allow acces to EFR
3606 3645
3607 WRITE_UART_REGISTER (uart, LCR, 0xBF); 3646 WRITE_UART_REGISTER (uart, LCR, 0xBF);
3608 3647
3609 // enable hardware assisted CTS 3648 // enable hardware assisted CTS
3610 3649
3611 SET_BIT (uart, EFR, AUTO_CTS_BIT); 3650 SET_BIT (uart, EFR, AUTO_CTS_BIT);
3612 3651
3613 WRITE_UART_REGISTER (uart, LCR, oldValue); 3652 WRITE_UART_REGISTER (uart, LCR, oldValue);
3614 #endif 3653 /* end Openmoko change */
3654
3615 if (uart->rts_level) 3655 if (uart->rts_level)
3616 uart->tx_stopped_by_driver = 1; 3656 uart->tx_stopped_by_driver = 1;
3657 } else {
3658 /* FreeCalypso addition: turn off OM-added Auto-CTS */
3659 SYS_UWORD8 oldValue;
3660
3661 oldValue = READ_UART_REGISTER (uart, LCR);
3662
3663 // LCR value to allow acces to EFR
3664
3665 WRITE_UART_REGISTER (uart, LCR, 0xBF);
3666
3667 // disable hardware assisted CTS
3668
3669 RESET_BIT (uart, EFR, AUTO_CTS_BIT);
3670
3671 WRITE_UART_REGISTER (uart, LCR, oldValue);
3617 } 3672 }
3618 3673
3619 /* 3674 /*
3620 * If the high watermark is reached, RTS is activated or XOFF is sent 3675 * If the high watermark is reached, RTS is activated or XOFF is sent
3621 * according to the flow control mode. Else, RTS is deactivated or XON 3676 * according to the flow control mode. Else, RTS is deactivated or XON
4327 /* If we have been stopped due to high RTS, we have to 4382 /* If we have been stopped due to high RTS, we have to
4328 * wake up application processor by IRQ via IO1 -HW */ 4383 * wake up application processor by IRQ via IO1 -HW */
4329 #ifdef CONFIG_TARGET_GTAMODEM 4384 #ifdef CONFIG_TARGET_GTAMODEM
4330 if (uart->tx_stopped_by_driver) 4385 if (uart->tx_stopped_by_driver)
4331 AI_SetBit(1); 4386 AI_SetBit(1);
4387 #elif defined(CONFIG_TANGO_MODEM)
4388 if (AI_Tango_pinmux[0] == 0x82 && uart->tx_stopped_by_driver)
4389 AI_SetBit(1);
4332 #endif 4390 #endif
4333 4391
4334 /* 4392 /*
4335 * If: 4393 * If:
4336 * - there is no break to send, 4394 * - there is no break to send,
4753 4811
4754 if (state & (1 << DCD)) { 4812 if (state & (1 << DCD)) {
4755 /* Turn on DCD */ 4813 /* Turn on DCD */
4756 #if (CHIPSET == 12) 4814 #if (CHIPSET == 12)
4757 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) | MDCD); 4815 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) | MDCD);
4816 #elif defined(CONFIG_TANGO_MODEM)
4817 if (AI_Tango_pinmux[1] & 0x08)
4818 AI_ResetBit (ARMIO_DCD);
4758 #else 4819 #else
4759 AI_ResetBit (ARMIO_DCD); 4820 AI_ResetBit (ARMIO_DCD);
4760 #endif 4821 #endif
4761 } else { 4822 } else {
4762 /* Turn off DCD */ 4823 /* Turn off DCD */
4763 #if (CHIPSET == 12) 4824 #if (CHIPSET == 12)
4764 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) & ~MDCD); 4825 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) & ~MDCD);
4826 #elif defined(CONFIG_TANGO_MODEM)
4827 if (AI_Tango_pinmux[1] & 0x08)
4828 AI_SetBit (ARMIO_DCD);
4765 #else 4829 #else
4766 AI_SetBit (ARMIO_DCD); 4830 AI_SetBit (ARMIO_DCD);
4767 #endif 4831 #endif
4768 } 4832 }
4769 } 4833 }
4789 4853
4790 if (state & (1 << SB)) { 4854 if (state & (1 << SB)) {
4791 /* Turn on DCD */ 4855 /* Turn on DCD */
4792 #if (CHIPSET == 12) 4856 #if (CHIPSET == 12)
4793 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) | MDCD); 4857 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) | MDCD);
4858 #elif defined(CONFIG_TANGO_MODEM)
4859 if (AI_Tango_pinmux[1] & 0x08)
4860 AI_ResetBit (ARMIO_DCD);
4794 #else 4861 #else
4795 AI_ResetBit (ARMIO_DCD); 4862 AI_ResetBit (ARMIO_DCD);
4796 #endif 4863 #endif
4797 } else { 4864 } else {
4798 /* Turn off DCD */ 4865 /* Turn off DCD */
4799 #if (CHIPSET == 12) 4866 #if (CHIPSET == 12)
4800 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) & ~MDCD); 4867 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) & ~MDCD);
4868 #elif defined(CONFIG_TANGO_MODEM)
4869 if (AI_Tango_pinmux[1] & 0x08)
4870 AI_SetBit (ARMIO_DCD);
4801 #else 4871 #else
4802 AI_SetBit (ARMIO_DCD); 4872 AI_SetBit (ARMIO_DCD);
4803 #endif 4873 #endif
4804 } 4874 }
4805 } 4875 }