--- a/src/cs/drivers/drv_app/uart/uartfax.c	Sun Jun 28 23:54:05 2020 +0000
+++ b/src/cs/drivers/drv_app/uart/uartfax.c	Mon Jun 29 00:27:13 2020 +0000
@@ -118,6 +118,10 @@
   #include "armio/armio.h"
 #endif
 
+#ifdef CONFIG_TANGO_MODEM
+extern SYS_UWORD8 AI_Tango_pinmux[4];
+#endif
+
 /* 
  * Maximal value for an unsigned 32 bits.
  */
@@ -2596,6 +2600,9 @@
             uart->tx_stopped_by_driver = 0;
             #ifdef CONFIG_TARGET_GTAMODEM
                 AI_ResetBit(1);
+            #elif defined(CONFIG_TANGO_MODEM)
+                if (AI_Tango_pinmux[0] == 0x82)
+                    AI_ResetBit(1);
             #endif
 
 #if ((CHIPSET != 5) && (CHIPSET != 6))
@@ -3021,9 +3028,15 @@
      * DCD should start HIGH (not asserted).
      */
 
+#ifdef CONFIG_TANGO_MODEM
+  if (AI_Tango_pinmux[1] & 0x08) {
+#endif
     *((volatile SYS_UWORD16 *) EXTENDED_MCU_REG) &= ~(1 << IO_DCD);
     AI_ConfigBitAsOutput (ARMIO_DCD);
     AI_SetBit (ARMIO_DCD);
+#ifdef CONFIG_TANGO_MODEM
+  }
+#endif
 
     /*
      * Select I/O for DTR and configure it as input.
@@ -3031,6 +3044,9 @@
      * or rising edge is selected according to the state of DTR.
      */
     
+#ifdef CONFIG_TANGO_MODEM
+  if (AI_Tango_pinmux[1] & 0x80) {
+#endif
     *((volatile SYS_UWORD16 *) ASIC_CONFIG_REG) &= ~(1 << IO_DTR);
     AI_ConfigBitAsInput (ARMIO_DTR);
     uart->dtr_level = AI_ReadBit (ARMIO_DTR);
@@ -3041,6 +3057,10 @@
         AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE);
         
     AI_UnmaskIT (ARMIO_MASKIT_GPIO);
+#ifdef CONFIG_TANGO_MODEM
+  } else
+    uart->dtr_level = 0;
+#endif
 
     /*
      * Reset the 2 indexes of the circular buffer of 2 elements.
@@ -3223,7 +3243,10 @@
 
     WRITE_UART_REGISTER (uart, IER, 0x00);
 
-#if UARTFAX_CLASSIC_DTR_DCD
+#ifdef CONFIG_TANGO_MODEM
+    if (AI_Tango_pinmux[1] & 0x80)
+      AI_MaskIT (ARMIO_MASKIT_GPIO);
+#elif UARTFAX_CLASSIC_DTR_DCD
     AI_MaskIT (ARMIO_MASKIT_GPIO);
 #elif (CHIPSET == 12)
     DISABLE_DSR_INTERRUPT (uart);
@@ -3369,6 +3392,9 @@
      * Read the state of DTR and select the edge.
      */
          
+#ifdef CONFIG_TANGO_MODEM
+  if (AI_Tango_pinmux[1] & 0x80) {
+#endif
     uart->dtr_level = AI_ReadBit (ARMIO_DTR);
     
     if (uart->dtr_level)
@@ -3377,6 +3403,11 @@
         AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE);
         
     AI_UnmaskIT (ARMIO_MASKIT_GPIO);
+#ifdef CONFIG_TANGO_MODEM
+  } else
+    uart->dtr_level = 0;
+#endif
+
 #elif (CHIPSET == 12)
     /*
      * Read the state of DTR - No need to reload MSR register since its value
@@ -3595,25 +3626,49 @@
             uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP);
             */
 #endif
-        
+
+        /*
+         * Openmoko made the change of enabling hardware assisted CTS
+         * flow control in the UART when RTS/CTS flow control is used -
+         * it is a change which we have retained in FreeCalypso -
+         * but they forgot to turn this hw mode off if RTS/CTS flow control
+         * is deselected at the application level.  We (FreeCalypso)
+         * are now fixing the latter defect ourselves.
+         */
         if (fcMode == fc_rts) {
-#if 1 // Dmitriy: enable hardware assisted CTS 
-            volatile SYS_UWORD8 oldValue;
+            /* begin Openmoko change */
+            SYS_UWORD8 oldValue;
 
             oldValue = READ_UART_REGISTER (uart, LCR);
-            
+
             // LCR value to allow acces to EFR
-     
+
             WRITE_UART_REGISTER (uart, LCR, 0xBF);
-            
+
             // enable hardware assisted CTS
-            
+
             SET_BIT (uart, EFR, AUTO_CTS_BIT);
-            
-            WRITE_UART_REGISTER (uart, LCR, oldValue);    
-#endif
+
+            WRITE_UART_REGISTER (uart, LCR, oldValue);
+            /* end Openmoko change */
+
             if (uart->rts_level)
                 uart->tx_stopped_by_driver = 1;
+        } else {
+            /* FreeCalypso addition: turn off OM-added Auto-CTS */
+            SYS_UWORD8 oldValue;
+
+            oldValue = READ_UART_REGISTER (uart, LCR);
+
+            // LCR value to allow acces to EFR
+
+            WRITE_UART_REGISTER (uart, LCR, 0xBF);
+
+            // disable hardware assisted CTS
+
+            RESET_BIT (uart, EFR, AUTO_CTS_BIT);
+
+            WRITE_UART_REGISTER (uart, LCR, oldValue);
         }
 
         /*
@@ -4329,6 +4384,9 @@
 	#ifdef CONFIG_TARGET_GTAMODEM
 	    if (uart->tx_stopped_by_driver)
 		AI_SetBit(1);
+	#elif defined(CONFIG_TANGO_MODEM)
+	    if (AI_Tango_pinmux[0] == 0x82 && uart->tx_stopped_by_driver)
+		AI_SetBit(1);
 	#endif
 
         /*
@@ -4755,6 +4813,9 @@
             /* Turn on DCD */
             #if (CHIPSET == 12)
                 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) | MDCD);
+            #elif defined(CONFIG_TANGO_MODEM)
+                if (AI_Tango_pinmux[1] & 0x08)
+                    AI_ResetBit (ARMIO_DCD);
             #else
                 AI_ResetBit (ARMIO_DCD);
             #endif
@@ -4762,6 +4823,9 @@
             /* Turn off DCD */
             #if (CHIPSET == 12)
                 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) & ~MDCD);
+            #elif defined(CONFIG_TANGO_MODEM)
+                if (AI_Tango_pinmux[1] & 0x08)
+                    AI_SetBit (ARMIO_DCD);
             #else
                 AI_SetBit (ARMIO_DCD);
             #endif
@@ -4791,6 +4855,9 @@
             /* Turn on DCD */
             #if (CHIPSET == 12)
                 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) | MDCD);
+            #elif defined(CONFIG_TANGO_MODEM)
+                if (AI_Tango_pinmux[1] & 0x08)
+                    AI_ResetBit (ARMIO_DCD);
             #else
                 AI_ResetBit (ARMIO_DCD);
             #endif
@@ -4798,6 +4865,9 @@
             /* Turn off DCD */
             #if (CHIPSET == 12)
                 WRITE_UART_REGISTER (uart, MCR, READ_UART_REGISTER(uart, MCR) & ~MDCD);
+            #elif defined(CONFIG_TANGO_MODEM)
+                if (AI_Tango_pinmux[1] & 0x08)
+                    AI_SetBit (ARMIO_DCD);
             #else
                 AI_SetBit (ARMIO_DCD);
             #endif