dnl This ld script source is fed through m4 in order to fill in
dnl those settings which depend on the configuration.
dnl Two include files are fed to m4 before this main body:
dnl the appropriate targets/*.m4 file defining the memory config
dnl of the hardware, and one of flash.m4 or xram.m4 to select
dnl the build type.

/*
 * FreeCalypso Selenite ld script for the Buildmem build
 */

ENTRY(_Firmware_boot_entry)

MEMORY {
ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1,
`	FLASH_OVERLAY : ORIGIN = 0, LENGTH = 0x2000')
ifelse(Buildmem,FLASH,
`	FLASH : ORIGIN = FLASHIMAGE_BASE_ADDR,
		LENGTH = CONFIG_FWFLASH_SIZE - FLASHIMAGE_BASE_ADDR')
	IRAM : ORIGIN = 0x00800000, LENGTH = CONFIG_IRAM_SIZE
	XRAM : ORIGIN = 0x01000000, LENGTH = CONFIG_XRAM_SIZE
}

SECTIONS {
dnl The following sections exist only in the flashImage build,
dnl and only on targets that use the Calypso boot ROM.
ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1,
`	/* Part of flash overlaid by the boot ROM */
	bootrom.overlay 0 : {
		*(bootrom.overlay)
	} > FLASH_OVERLAY

	/* code that enables the boot ROM and jumps to it */
	bootrom.switch : {
		*(bootrom.switch)
	} > IRAM AT> FLASH_OVERLAY
	__romswitch_ram_addr = ADDR(bootrom.switch);
	__romswitch_flash_addr = LOADADDR(bootrom.switch);
	__romswitch_size = SIZEOF(bootrom.switch);
')dnl

define(`INTTEXT_BASE_ADDR',
    ifelse(Buildmem,FLASH,FLASHIMAGE_BASE_ADDR,`/* no fixed address */'))dnl

	/* boot entry code, going into flash or XRAM emulating flash */
	.inttext INTTEXT_BASE_ADDR : {
		*(.inttext)
	} > Buildmem

	/* copy-to-IRAM code */
	iram.text 0x80001C : {
		/* the 7 exception and interrupt vectors @ 0x80001C */
		*(.ramvecs)
		*_ir.a:(.text*)
		*_int.a:(.text*)
		*_intram.a:(.text*)
		*osx_na7_db.a:(.text*)
		*tpudrv.a:(.text*)
		*drivers_flash.a:niq32.o(.text*)
		*sim_drv.a:sim32.o(.text*)
		*libc.a:(.text*)
		*libgcc.a:(.text*)
	} > IRAM Put_in_flash
ifelse(Buildmem,FLASH,
`	__iramtext_ram_addr = ADDR(iram.text);
	__iramtext_flash_addr = LOADADDR(iram.text);
	__iramtext_size = SIZEOF(iram.text);
')dnl

	/* XIP code, going into flash or XRAM emulating flash */
	xip.text : {
		*(.text*)
		/* let's put the ARM->Thumb veneers in the XIP section */
		*(.glue_7)
	} > Buildmem

	/* all .rodata will stay in flash */
	.rodata : {
		*(.rodata*)
	} > Buildmem

	/*
	 * All .data will go into XRAM.
	 * For the flash build we'll have a step that copies
	 * the .data section from flash to XRAM; for the RAM-only
	 * build it goes directly into XRAM and stays there.
	 */
	.data : {
		*(.data*)
	} > XRAM Put_in_flash
ifelse(Buildmem,FLASH,
`	__initdata_ram_addr = ADDR(.data);
	__initdata_flash_addr = LOADADDR(.data);
	__initdata_size = SIZEOF(.data);
')dnl

	.bss_dar (NOLOAD) : {
		*dar_gbl_var.a:(.bss* COMMON)
	} > XRAM

	/* we have two kinds of BSS: internal and external */
	int.bss (NOLOAD) : {
		*(.l1s_global)
		*_ir.a:(.bss* COMMON)
		*_int.a:(.bss* COMMON)
		*_intram.a:(.bss* COMMON)
		*osx_na7_db.a:(.bss* COMMON)
		*tpudrv.a:(.bss* COMMON)
		*libc.a:(.bss* COMMON)
		*libgcc.a:(.bss* COMMON)
		*(.API_HISR_stack)
		. = ALIGN(4);
	} > IRAM
	__intbss_start = ADDR(int.bss);
	__intbss_size = SIZEOF(int.bss);

	ext.bss (NOLOAD) : {
		*(.bss* COMMON)
		. = ALIGN(4);
	} > XRAM
	__extbss_start = ADDR(ext.bss);
	__extbss_size = SIZEOF(ext.bss);

	int.stack (NOLOAD) : ALIGN(8) {
		/* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
		_Stack_segment_start = .;
		. += 0xB00;
		_Stack_segment_end = .;

		_iram_end = .;
	} > IRAM

	ext.stack (NOLOAD) : ALIGN(8) {
		/* Stack for abort and/or undefined modes. */
		. += 512;
		_Except_Stack_SP = .;

		/* Leave 38 32bit words for state saving on exceptions. */
		xdump_buffer = .;
		. += 38 * 4;

		_xram_end = .;
	} > XRAM
}