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.../main/gcc/bootentry.S: the literal pool needs to be arranged the way TI had it
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 20 Jul 2018 23:39:27 +0000
parents 95ef11e76c5b
children
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/*
 * These 7 branch instructions, corresponding to ARM exception and interrupt
 * vectors, will be placed in different sections depending on the flashImage
 * vs. ramImage configuration and which target we build for; this little
 * snippet file will be #included where it is needed.
 */

	b	_arm_undefined
	b	_arm_swi
	b	_arm_abort_prefetch
	b	_arm_abort_data
	b	_arm_reserved
	b	_INT_IRQ
	b	_INT_FIQ