FreeCalypso > hg > fc-selenite
changeset 210:b81101e50fc6
uartfax.c: pull from Tourmaline (GTM900 RI output)
uartfax.c will now be exactly the same between Magnetite, Selenite
and Tourmaline.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sat, 24 Oct 2020 17:46:26 +0000 |
| parents | d0547d47260a |
| children | 4035c19073aa |
| files | src/cs/drivers/drv_app/uart/uartfax.c |
| diffstat | 1 files changed, 288 insertions(+), 273 deletions(-) [+] |
line wrap: on
line diff
--- a/src/cs/drivers/drv_app/uart/uartfax.c Tue Oct 20 01:58:41 2020 +0000 +++ b/src/cs/drivers/drv_app/uart/uartfax.c Sat Oct 24 17:46:26 2020 +0000 @@ -29,9 +29,9 @@ * 1 DCD DCD output 1 1, 6 and 4 are connected together on DB9 * 2 RX TX output 2 RX TX2 output * 3 TX RX input 3 TX RX2 input - * 4 DTR DSR input 4 + * 4 DTR DSR input 4 * 5 GND 5 GND - * 6 NC 6 + * 6 NC 6 * 7 RTS CTS input 7 RTS CTS2 input * 8 CTS RTS output 8 CTS RTS2 output * 9 NC 9 NC @@ -48,9 +48,9 @@ * 1 DCD I/O 2 output 1 1, 6 and 4 are connected together on DB9 * 2 RX TX output 2 RX TX2 output * 3 TX RX input 3 TX RX2 input - * 4 DTR I/O 3 input 4 + * 4 DTR I/O 3 input 4 * 5 GND 5 GND - * 6 NC 6 + * 6 NC 6 * 7 RTS CTS input 7 RTS CTS2 input * 8 CTS RTS output 8 CTS RTS2 output * 9 NC 9 NC @@ -75,7 +75,7 @@ * 9 NC 9 NC * */ - + #include "swconfig.cfg" #include "l1sw.cfg" @@ -122,7 +122,7 @@ extern SYS_UWORD8 AI_Tango_pinmux[4]; #endif -/* +/* * Maximal value for an unsigned 32 bits. */ @@ -135,7 +135,7 @@ * TLR is used to program the RX FIFO trigger levels. FCR[7:4] are not used. * No trigger level used for TX FIFO. THR_IT generated on TX FIFO empty. */ - + #define RX_FIFO_TRIGGER_LEVEL (12 << 4) @@ -190,7 +190,7 @@ /* * Enhanced feature register. */ - + #define ENHANCED_FEATURE_BIT (4) /* Use RESET_BIT and SET_BIT macros. */ #define AUTO_CTS_BIT (7) /* Transmission is halted when the CTS pin is high (inactive). */ @@ -308,15 +308,15 @@ /* * 3 HISR are used to avoid to execute operations from the LISR. */ - + #define RX_HISR_PRIORITY (2) // NGENGE increase hisr stack otherwise overflows with multiple callbacks -//#define RX_HISR_STACK_SIZE (512) /* Bytes. */ -#define RX_HISR_STACK_SIZE (768) /* Bytes. */ +//#define RX_HISR_STACK_SIZE (512) /* Bytes. */ +#define RX_HISR_STACK_SIZE (768) /* Bytes. */ @@ -326,14 +326,14 @@ // NGENGE increase hisr stack otherwise overflows with multiple callbacks -//#define TX_HISR_STACK_SIZE (512) /* Bytes. */ -#define TX_HISR_STACK_SIZE (768) /* Bytes. */ +//#define TX_HISR_STACK_SIZE (512) /* Bytes. */ +#define TX_HISR_STACK_SIZE (768) /* Bytes. */ #define V24_HISR_PRIORITY (2) -#define V24_HISR_STACK_SIZE (512) /* Bytes. */ +#define V24_HISR_STACK_SIZE (512) /* Bytes. */ /* * When the break interrupt indicator (BI) is set in the line status register @@ -417,16 +417,16 @@ * Low and high watermarks for the RX buffer. If it is enabled, the flow * control is activated or deactivated according to these values. * The high watermark value allows to copy an array filled with the RX FIFO - * into the RX buffer. + * into the RX buffer. */ #define RX_LOW_WATERMARK(RX_BUFFER_SIZE) (FIFO_SIZE) #define RX_HIGH_WATERMARK(RX_BUFFER_SIZE) ((RX_BUFFER_SIZE) - 2 * FIFO_SIZE) -/* +/* * This macro allows to know if the RX buffer is full. It must be called only - * from the RX HISR. If it is called from the application, the rx_in and - * rx_fifo_in pointers may be updated if a RX interrupt occurs or if the + * from the RX HISR. If it is called from the application, the rx_in and + * rx_fifo_in pointers may be updated if a RX interrupt occurs or if the * RX HISR is activated. */ @@ -460,7 +460,7 @@ /* * HISR executed from the RX/TX interrupt handler. */ - + NU_HISR rx_hisr_ctrl_block; NU_HISR tx_hisr_ctrl_block; NU_HISR v24_hisr_ctrl_block; @@ -468,20 +468,20 @@ char rx_hisr_stack[RX_HISR_STACK_SIZE]; char tx_hisr_stack[TX_HISR_STACK_SIZE]; char v24_hisr_stack[V24_HISR_STACK_SIZE]; - + /* * 2 arrays are used to store bytes read in RX FIFO. A UART RX interrupt * may occur while executing RX operations in RX HISR. To avoid overwriting * the array in which received bytes are stored, a second array is used. */ - + SYS_UWORD8 *rx_buffer_used_by_rx_lisr; SYS_UWORD8 *rx_buffer_used_by_rx_hisr; SYS_UWORD8 rx_fifo_byte_1[FIFO_SIZE]; SYS_UWORD8 rx_fifo_byte_2[FIFO_SIZE]; SYS_UWORD16 bytes_in_rx_buffer_1; SYS_UWORD16 bytes_in_rx_buffer_2; - + /* * RX and TX buffers. * One character is not used in each buffer to allow to know if the buffer @@ -545,7 +545,7 @@ char break_hisr_stack[BREAK_HISR_STACK_SIZE]; NU_TIMER break_timer_ctrl_block; UNSIGNED baudrate; - UNSIGNED autobauding; + UNSIGNED autobauding; UNSIGNED bits_per_char; /* Including start, stop and parity bits. */ UNSIGNED break_length; /* In bytes. */ UNSIGNED time_without_character; @@ -584,14 +584,14 @@ * The level of DTR is saved to provide the level detected on Rx interrupt * or DTR interrupt in the 'state' parameter of the user's Rx callback * function. - */ + */ SYS_BOOL dtr_change_detected[2]; SYS_UWORD8 dtr_level_saved[2]; SYS_UWORD8 index_it; SYS_UWORD8 index_hisr; -#endif /* BOARD 8 or 9 or 40 or 41 or CHIPSET 12 */ - +#endif /* BOARD 8 or 9 or 40 or 41 or CHIPSET 12 */ + SYS_BOOL reading_suspended; SYS_BOOL writing_suspended; SYS_BOOL rd_call_from_hisr_in_progress; @@ -685,7 +685,7 @@ 0 /* 812500 baud: not supported. */ }; -static const SYS_UWORD8 dlh[] = +static const SYS_UWORD8 dlh[] = { 0, /* Auto baud: */ 42, /* 75 baud. */ @@ -734,12 +734,12 @@ }; - + /******************************************************************************* * * get_bytes_in_rx_buffer - * + * * Purpose : Gets the number of bytes in the RX buffer. * * Arguments: In : uart: Pointer on the UART structure. @@ -769,7 +769,7 @@ /******************************************************************************* * * get_bytes_in_tx_buffer - * + * * Purpose : Gets the number of bytes in the TX buffer. * * Arguments: In : uart: Pointer on the UART structure. @@ -799,7 +799,7 @@ /******************************************************************************* * * compute_break_time - * + * * Purpose : Computes a number of TDMA from 3 parameters: * - baudrate, * - bits per character including start bit, stop bits and parity, @@ -836,7 +836,7 @@ /******************************************************************************* * * update_reading_callback - * + * * Purpose : Updates the sizes array and the addresses array and get and builds * the state parameter defined in UAF_GetLineState to call the * readOutFunc function. @@ -866,7 +866,7 @@ */ rx_in = uart->rx_in; - + if (uart->rx_out < rx_in) { fragments_number = 1; @@ -881,7 +881,7 @@ bytes_in_rx_buffer = uart->rd_size_before_call[0]; } else if (rx_in == uart->rx_out) { /* RX buffer empty. */ - + fragments_number = 1; uart->rd_address[0] = uart->rx_out; @@ -892,9 +892,9 @@ uart->rd_size_after_call[1] = 0; bytes_in_rx_buffer = 0; - + } else { - + fragments_number = 2; uart->rd_address[0] = uart->rx_out; @@ -970,7 +970,7 @@ if (uart->flow_control_mode == fc_rts) state |= (((SYS_UWORD32) uart->rts_level) << X); - + else if ((uart->flow_control_mode == fc_xoff) && (uart->tx_stopped_by_application || uart->tx_stopped_by_driver)) @@ -993,7 +993,7 @@ /******************************************************************************* * * update_writing_callback - * + * * Purpose : Updates the sizes array and the addresses array to call the * writeInFunc function. * @@ -1019,7 +1019,7 @@ */ tx_out = uart->tx_out; - + if (uart->tx_in < tx_out) { fragments_number = 1; @@ -1031,14 +1031,14 @@ uart->wr_size_before_call[1] = 0; uart->wr_size_after_call[1] = 0; - + } else if (tx_out == &(uart->tx_buffer[0])) { fragments_number = 1; - + uart->wr_address[0] = uart->tx_in; uart->wr_size_before_call[0] = - uart->buffer_size - + uart->buffer_size - (SYS_UWORD16) (uart->tx_in - &(uart->tx_buffer[0])); uart->wr_size_after_call[0] = uart->wr_size_before_call[0]; @@ -1046,12 +1046,12 @@ uart->wr_size_after_call[1] = 0; } else { - + fragments_number = 2; uart->wr_address[0] = uart->tx_in; uart->wr_size_before_call[0] = - uart->buffer_size + 1 - + uart->buffer_size + 1 - (SYS_UWORD16) (uart->tx_in - &(uart->tx_buffer[0])); uart->wr_size_after_call[0] = uart->wr_size_before_call[0]; @@ -1080,7 +1080,7 @@ /******************************************************************************* * * stop_break - * + * * Purpose : The timer is activated to expire when a time corresponding to the * sending time of 2 characters at least has elapsed. After a break, * no character may be sent during this period. @@ -1106,7 +1106,7 @@ /* * Disable sleep mode. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); #endif @@ -1122,7 +1122,7 @@ /******************************************************************************* * * hisr_start_break - * + * * Purpose : Enables the timer used to control the time without character. * * Arguments: In : none @@ -1155,8 +1155,8 @@ /******************************************************************************* * * stop_receiver - * - * Purpose : Activates DTR or RTS or sends XOFF. + * + * Purpose : Activates DTR or RTS or sends XOFF. * * Arguments: In : uart: Pointer on the UART structure. * Out: none @@ -1172,7 +1172,7 @@ /* * Disable sleep mode. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); #endif @@ -1197,7 +1197,7 @@ /* * Unmask Tx interrupt. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI); break; @@ -1207,7 +1207,7 @@ /******************************************************************************* * * start_receiver - * + * * Purpose : Deactivates DTR or RTS or sends XON. * * Arguments: In : uart: Pointer on the UART structure. @@ -1224,7 +1224,7 @@ /* * Disable sleep mode. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); #endif @@ -1249,7 +1249,7 @@ /* * Unmask Tx interrupt. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI); break; @@ -1259,7 +1259,7 @@ /******************************************************************************* * * add_esc_seq_char_in_rx_buffer - * + * * Purpose : Writes one escape sequence character in the RX buffer. * * Arguments: In : uart: Pointer on the UART structure. @@ -1289,7 +1289,7 @@ /******************************************************************************* * * analyze_guard_period_timer_expiration - * + * * Purpose : According to the state of the escape sequence detection, 1 or 2 * escape sequence characters may be written into the TX buffer or * the escape sequence is declared as detected. @@ -1301,7 +1301,7 @@ * Arguments: In : id: parameter not used. * Out: none * - * Returns : none + * Returns : none * ******************************************************************************/ @@ -1314,44 +1314,44 @@ uart = &uart_parameters; switch (uart->esc_seq_detection_state) { - + case ONE_CHAR_DETECTED: - + /* * 1 escape sequence character has been detected. The guard period has * ellapsed. This character is written into the TX buffer. */ - + add_esc_seq_char_in_rx_buffer (uart); break; - + case TWO_CHARS_DETECTED: - + /* * 2 escape sequence characters have been detected. The guard period has * ellapsed. These characters are written into the TX buffer. */ - + add_esc_seq_char_in_rx_buffer (uart); add_esc_seq_char_in_rx_buffer (uart); break; - + case THREE_CHARS_DETECTED: /* * 3 escape sequence characters have been detected and the guard period * has ellapsed. The escape sequence is detected. - */ - + */ + uart->esc_seq_received = 1; *(uart->state) |= (1 << ESC); - + break; } - + uart->esc_seq_detection_state = NO_ESCAPE_SEQUENCE; - + /* * If the high watermark is reached, RTS is activated or XOFF is sent * according to the flow control mode. @@ -1403,13 +1403,13 @@ /******************************************************************************* * * stop_guard_period_timer - * + * * Purpose : Stops the timer used to detect the guard period expiration. * * Arguments: In : uart: Pointer on the UART structure. * Out: none * - * Returns : none + * Returns : none * ******************************************************************************/ @@ -1423,13 +1423,13 @@ /******************************************************************************* * * start_guard_period_timer - * + * * Purpose : Starts a timer which expires if the guard period has ellapsed. * * Arguments: In : uart: Pointer on the UART structure. * Out: none * - * Returns : none + * Returns : none * ******************************************************************************/ @@ -1452,7 +1452,7 @@ /******************************************************************************* * * detect_escape_sequence - * + * * Purpose : The state machine used to detect an escape sequence is updated * according to the array of bytes to analyse. If the state machine * goes to the initial state due to a break in the sequence @@ -1461,7 +1461,7 @@ * Arguments: In : uart: Pointer on the UART structure. * Out: none * - * Returns : 0: Break in detection or a sequence has been detected. + * Returns : 0: Break in detection or a sequence has been detected. * 1: A sequence may be detected. * ******************************************************************************/ @@ -1523,7 +1523,7 @@ case 1: if (*rx_fifo_byte++ == uart->esc_seq_character) { - + uart->esc_seq_detection_state = ONE_CHAR_DETECTED; start_guard_period_timer (uart); detection_result = 1; @@ -1535,12 +1535,12 @@ if ((*rx_fifo_byte++ == uart->esc_seq_character) && (*rx_fifo_byte++ == uart->esc_seq_character)) { - + uart->esc_seq_detection_state = TWO_CHARS_DETECTED; start_guard_period_timer (uart); detection_result = 1; } - + break; case 3: @@ -1548,16 +1548,16 @@ if ((*rx_fifo_byte++ == uart->esc_seq_character) && (*rx_fifo_byte++ == uart->esc_seq_character) && (*rx_fifo_byte++ == uart->esc_seq_character)) { - + uart->esc_seq_detection_state = THREE_CHARS_DETECTED; start_guard_period_timer (uart); detection_result = 1; } - + break; default: - + /* * No action. */ @@ -1587,9 +1587,9 @@ case 1: if (*rx_fifo_byte++ == uart->esc_seq_character) { - + uart->esc_seq_detection_state = TWO_CHARS_DETECTED; - detection_result = 1; + detection_result = 1; } break; @@ -1598,13 +1598,13 @@ if ((*rx_fifo_byte++ == uart->esc_seq_character) && (*rx_fifo_byte++ == uart->esc_seq_character)) { - + start_guard_period_timer (uart); /* Reset the timer. */ - + uart->esc_seq_detection_state = THREE_CHARS_DETECTED; - detection_result = 1; + detection_result = 1; } - + break; default: @@ -1646,11 +1646,11 @@ if (*rx_fifo_byte++ == uart->esc_seq_character) { start_guard_period_timer (uart); /* Reset the timer. */ - + uart->esc_seq_detection_state = THREE_CHARS_DETECTED; detection_result = 1; } - + break; default: @@ -1700,7 +1700,7 @@ /******************************************************************************* * * send_break - * + * * Purpose : This function may only called if the TX FIFO is empty. * Null characters are written in the TX FIFO. The number of bytes to * write has been defined with UAF_SetLineState. Enables the break @@ -1732,7 +1732,7 @@ WRITE_UART_REGISTER ( uart, LCR, READ_UART_REGISTER (uart, LCR) | BREAK_CONTROL); - + #if ((CHIPSET != 5) && (CHIPSET != 6)) /* * Re-enable sleep mode. @@ -1759,9 +1759,9 @@ /******************************************************************************* * * build_rx_fifo_array - * + * * Purpose : Reads the RX FIFO to build an array with bytes read. - * A byte is written in this array if no error is detected. + * A byte is written in this array if no error is detected. * * Arguments: In : uart: Pointer on the UART structure. * Out: none @@ -1785,20 +1785,20 @@ x = 1; bytes_received = 0; - - + + /* * Switch to the other buffer. */ - + first_byte = uart->rx_buffer_used_by_rx_lisr; if (first_byte == &(uart->rx_fifo_byte_1[0])) { - + first_byte = &(uart->rx_fifo_byte_2[0]); bytes_in_rx_buffer = &(uart->bytes_in_rx_buffer_2); - + } else { - + first_byte = &(uart->rx_fifo_byte_1[0]); bytes_in_rx_buffer = &(uart->bytes_in_rx_buffer_1); } @@ -1806,30 +1806,30 @@ current_byte = first_byte; if (*bytes_in_rx_buffer) { - + /* The Rx buffer is not empty and is being used by HISR ! */ /* Hence stop the flow control */ - stop_receiver (uart); + stop_receiver (uart); /* * Reset LCR[7] (DLAB) to have access to the RBR, THR and IER registers. */ WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); - + /* Mask The Rx and interrupt */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~(ERBI | EDSSI)); - + uart->rx_stopped_by_lisr = 1; return (bytes_received); - + } uart->rx_buffer_used_by_rx_lisr = first_byte; - + status = READ_UART_REGISTER (uart, LSR); /* @@ -1862,13 +1862,13 @@ */ if (status & BI) { - + uart->break_received = 1; *(uart->state) |= ((1 << BRK) | (MINIMAL_BREAK_LENGTH << BRKLEN)); } - } else /* No error */ + } else /* No error */ current_byte++; status = READ_UART_REGISTER (uart, LSR); @@ -1882,24 +1882,24 @@ */ if (!bytes_received) { - + if (uart->rx_buffer_used_by_rx_lisr == &(uart->rx_fifo_byte_1[0])) uart->rx_buffer_used_by_rx_lisr = &(uart->rx_fifo_byte_2[0]); - + else uart->rx_buffer_used_by_rx_lisr = &(uart->rx_fifo_byte_1[0]); } if (bytes_received > uart->max_rx_fifo_level) uart->max_rx_fifo_level = bytes_received; - + return (bytes_received); } /******************************************************************************* * * empty_rx_fifo - * + * * Purpose : Read the RX FIFO. * * Arguments: In : uart: Pointer on the UART structure. @@ -1930,12 +1930,12 @@ /******************************************************************************* * * hisr_execute_rx_operations - * + * * Purpose : If an escape sequence is detected or if a break in the detection - * has occured RX FIFO bytes are written in the RX buffer. + * has occured RX FIFO bytes are written in the RX buffer. * If the software flow control is used bytes are analyzed to know * if a XON or a XOFF character is received to stop or start the - * transmitter. + * transmitter. * If a flow control is used and if the high watermark of the RX * buffer is reached the receiver is stopped. * If the RX threshold level is reached the callback mechanism is @@ -1961,7 +1961,7 @@ t_uart *uart; uart = &uart_parameters; - + /* * Since new characters have been received, the sleep timer is reset then * restarted preventing the system to enter deep-sleep for a new period of @@ -1976,19 +1976,19 @@ #endif xon_xoff_detected = 0; - + /* * Switch to the other buffer. */ - + current_byte = uart->rx_buffer_used_by_rx_hisr; if (current_byte == &(uart->rx_fifo_byte_1[0])) { - + current_byte = &(uart->rx_fifo_byte_2[0]); bytes_read = uart->bytes_in_rx_buffer_2; - + } else { - + current_byte = &(uart->rx_fifo_byte_1[0]); bytes_read = uart->bytes_in_rx_buffer_1; } @@ -2010,16 +2010,16 @@ wrap_around_counter = uart->buffer_size + 1 - (SYS_UWORD16) (uart->rx_in - &(uart->rx_buffer[0])); - + if (uart->flow_control_mode == fc_xoff) { - + /* * For SW Flow Control, need to further investigate the processing * in order to improve the performance of the driver, and in order * to avoid managing the wrap around of the circular buffer each * time a character is copied. */ - + while (bytes_read && bytes_free_in_rx_buffer) { /* @@ -2041,7 +2041,7 @@ /* * Disable sleep mode. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); #endif @@ -2049,21 +2049,21 @@ /* * Unmask Tx interrupt. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI); } else { - + *(uart->rx_in++) = *current_byte; wrap_around_counter--; if (!wrap_around_counter) { - + uart->rx_in = &(uart->rx_buffer[0]); wrap_around_counter = uart->buffer_size + 1; } - + bytes_free_in_rx_buffer--; } @@ -2071,18 +2071,18 @@ bytes_read--; } } else { /* No Flow Control or HW Flow Control */ - + /* * Figure out the most restricting condition. */ bytes_to_copy = Min3 (bytes_free_in_rx_buffer, wrap_around_counter, bytes_read); - + /* * Copy characters into the circular Rx buffer. */ - + memcpy (uart->rx_in, current_byte, bytes_to_copy); /* @@ -2090,10 +2090,10 @@ * if (bytes_read = 0) OR * (bytes_free_in_rx_buffer = 0) => No more characters to copy. */ - + bytes_free_in_rx_buffer -= bytes_to_copy; bytes_read -= bytes_to_copy; - + wrap_around_counter -= bytes_to_copy; if (!wrap_around_counter) uart->rx_in = &(uart->rx_buffer[0]); @@ -2125,12 +2125,12 @@ memcpy (uart->rx_in, current_byte, bytes_to_copy); uart->rx_in += bytes_to_copy; - + /* * bytes_free_in_rx_buffer not updated since not used anymore. */ bytes_read -= bytes_to_copy; - + } else { bytes_read = 0; @@ -2196,24 +2196,24 @@ WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); - + /* Mask The Rx and Modem status interrupt */ WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~(ERBI | EDSSI)); - + if ((uart->rx_buffer_used_by_rx_hisr) == &(uart->rx_fifo_byte_1[0])) { - + uart->bytes_in_rx_buffer_1 = 0; - + } else { - + uart->bytes_in_rx_buffer_2 = 0; } - + WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); - + /* Unmask The Rx and Modem status interrupt*/ WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) | @@ -2221,23 +2221,23 @@ if(uart->rx_stopped_by_lisr ) { if (!uart->rx_stopped_by_driver) { - + uart->rx_stopped_by_lisr = 0; - + /* * Reset LCR[7] (DLAB) to have access to the RBR, THR and IER registers. */ WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); - + /* UnMask The Rx interrupt */ WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) | (ERBI | EDSSI)); - + start_receiver (uart); - + } } @@ -2246,7 +2246,7 @@ /******************************************************************************* * * hisr_execute_v24_operations - * + * * Purpose : The user's function is called if all conditions to call it are * fulfiled. * @@ -2285,7 +2285,7 @@ /******************************************************************************* * * hisr_execute_tx_operations - * + * * Purpose : Writes bytes from the TX buffer to the TX FIFO. * The user's function is called if all conditions to call it are * fulfiled. @@ -2321,9 +2321,9 @@ if (READ_UART_REGISTER (uart, LSR) & THRE) { bytes_in_tx_fifo = 0; - + /* - * A request to send a XON/XOFF character may have been done by the + * A request to send a XON/XOFF character may have been done by the * RX interrupt handler. The byte can be written because we are sure * that the TX FIFO is not full. */ @@ -2453,7 +2453,7 @@ /* * Unmask Tx interrupt. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI); @@ -2481,7 +2481,7 @@ /******************************************************************************* * * read_rx_fifo - * + * * Purpose : Reads the RX FIFO. If the driver is enabled bytes are written in * an array to be analyzed by the RX HISR. * @@ -2501,22 +2501,22 @@ * interrupt else bytes received are written into an array which will be * analyzed from the RX HISR. */ - + if (DRIVER_DISABLED (uart)) empty_rx_fifo (uart); else if (build_rx_fifo_array (uart)){ (void) NU_Activate_HISR (&(uart->rx_hisr_ctrl_block)); - + } - + } /******************************************************************************* * * check_v24_input_lines - * + * * Purpose : Check the V.24 input lines. According to the states of the input * lines and to the flow control mode selected, the transmitter is * enabled or disabled. The reading callback function is called if @@ -2566,19 +2566,19 @@ * the change of state of DTR must be copied into the RX buffer before to * call it. */ - + if (READ_UART_REGISTER (uart, LSR) & DR) { /* If Rx FIFO is not empty */ - + /* * The Rx FIFO will be read to fill one of the two buffers and the Rx * HISR will be activated. */ - + uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */ uart->dtr_change_detected[uart->index_it] = 1; uart->dtr_level_saved[uart->index_it] = uart->dtr_level; read_rx_fifo (uart); - + } else v24_input_line_changed = 1; } @@ -2590,13 +2590,13 @@ */ if (uart->flow_control_mode == fc_rts) { - + if (uart->rts_level) { uart->tx_stopped_by_driver = 1; - } + } else { - + uart->tx_stopped_by_driver = 0; #ifdef CONFIG_TARGET_GTAMODEM AI_ResetBit(1); @@ -2609,7 +2609,7 @@ /* * Disable sleep mode. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); #endif @@ -2631,7 +2631,7 @@ /******************************************************************************* * * fill_tx_fifo - * + * * Purpose : If the TX buffer is not empty, and if there is no break in * progress, bytes are written into the TX FIFO until the TX FIFO is * full or the TX buffer is empty. Else, if there is a break to send @@ -2643,7 +2643,7 @@ * FIFO. The number of bytes has been defined previously with the * UAF_SetLineState function. The break condition is enabled. * When the TX FIFO and the transmitter shift register (TSR) are both - * empty and if a break is in progress, the break condition is + * empty and if a break is in progress, the break condition is * disabled. * When bytes are written from the TX buffer to the TX FIFO, the * writing callback function is called if it is installed and if all @@ -2681,7 +2681,7 @@ */ if (!uart->break_in_progress) - (void) NU_Activate_HISR (&(uart->tx_hisr_ctrl_block)); + (void) NU_Activate_HISR (&(uart->tx_hisr_ctrl_block)); else { @@ -2699,7 +2699,7 @@ /******************************************************************************* * * UAF_Init - * + * * Purpose : Initializes the UART hardware and installs interrupt handlers. * The parameters are set to the default values: * - 19200 baud, @@ -2743,7 +2743,7 @@ * A return is used to simplify the code if an error occurs. * All stacks are entirely filled with the pattern 0xFE. */ - + memset (&(uart->rx_hisr_stack[0]), 0xFE, RX_HISR_STACK_SIZE); if (NU_Create_HISR (&(uart->rx_hisr_ctrl_block), @@ -2830,7 +2830,7 @@ */ uart->baudrate = baudrate_value[FD_BAUD_19200]; - uart->autobauding = 0; + uart->autobauding = 0; uart->bits_per_char = 10; /* @@ -2842,10 +2842,10 @@ /* * Select the current array used to store received bytes. */ - + uart->rx_buffer_used_by_rx_lisr = &(uart->rx_fifo_byte_2[0]); uart->rx_buffer_used_by_rx_hisr = &(uart->rx_fifo_byte_2[0]); - + /* * RX and TX buffers. */ @@ -2929,7 +2929,7 @@ /* * Reset UART mode configuration. */ - + WRITE_UART_REGISTER (uart, MDR1, RESET_DEFAULT_STATE | IR_SLEEP_DISABLED | SIR_TX_WITHOUT_ACREG2 | @@ -2939,7 +2939,7 @@ * FIFO configuration. * EFR[4] = 1 to allow to program FCR[5:4] and MCR[7:5]. */ - + WRITE_UART_REGISTER (uart, LCR, 0xBF); SET_BIT (uart, EFR, ENHANCED_FEATURE_BIT); @@ -2954,7 +2954,7 @@ * Program the trigger levels. * MCR[6] must be set to 1. */ - + SET_BIT (uart, MCR, TCR_TLR_BIT); WRITE_UART_REGISTER (uart, TCR, 0x0F); WRITE_UART_REGISTER (uart, TLR, RX_FIFO_TRIGGER_LEVEL); @@ -2966,7 +2966,7 @@ WRITE_UART_REGISTER ( uart, SCR, READ_UART_REGISTER (uart, SCR) | TX_EMPTY_CTL_IT); - + /* * Program the FIFO control register. Bit 0 must be set when other FCR bits * are written to or they are not programmed. @@ -2993,7 +2993,7 @@ /* * Select UART mode. */ - + WRITE_UART_REGISTER (uart, MDR1, UART_MODE | IR_SLEEP_DISABLED | SIR_TX_WITHOUT_ACREG2 | @@ -3016,7 +3016,7 @@ * DCD: I/O 2 (output) * DTR: I/O 3 (input) */ - + #define EXTENDED_MCU_REG (0xFFFEF006) /* Extended MCU register */ #define ASIC_CONFIG_REG (0xFFFEF008) /* Asic Configuration register */ @@ -3043,7 +3043,7 @@ * An interrupt is used to detect a change of state of DTR. Falling edge * or rising edge is selected according to the state of DTR. */ - + #ifdef CONFIG_TANGO_MODEM if (AI_Tango_pinmux[1] & 0x80) { #endif @@ -3055,7 +3055,7 @@ AI_SelectIOForIT (ARMIO_DTR, ARMIO_FALLING_EDGE); else AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE); - + AI_UnmaskIT (ARMIO_MASKIT_GPIO); #ifdef CONFIG_TANGO_MODEM } else @@ -3066,7 +3066,7 @@ * Reset the 2 indexes of the circular buffer of 2 elements. * The circular buffer does not need to be initialized. */ - + uart->index_it = 0; uart->index_hisr = 0; #elif (CHIPSET == 12) @@ -3092,11 +3092,11 @@ * Reset the 2 indexes of the circular buffer of 2 elements. * The circular buffer does not need to be initialized. */ - + uart->index_it = 0; uart->index_hisr = 0; #endif /* BOARD == 8, 9, 40 or 41, CHIPSET == 12 */ - + /* * Unmask RX interrupt and the modem status interrupt. */ @@ -3117,7 +3117,7 @@ /******************************************************************************* * * UAF_Enable - * + * * Purpose : The functionalities of the UART driver are disabled or enabled. * In the deactivated state, all information about the communication * parameters should be stored and recalled if the driver is again @@ -3156,13 +3156,13 @@ /* * There is no case where FD_INTERNAL_ERR may be returned. */ - + uart = &uart_parameters; if (enable) { uart->rx_stopped_by_driver = 0; - + ENABLE_DRIVER (uart); start_receiver (uart); @@ -3183,7 +3183,7 @@ /******************************************************************************* * * UAF_SetComPar - * + * * Purpose : Sets up the communication parameters: baud rate, bits per * character, number of stop bits, parity. * @@ -3255,7 +3255,7 @@ /* * Reset UART mode configuration. */ - + WRITE_UART_REGISTER (uart, MDR1, RESET_DEFAULT_STATE | IR_SLEEP_DISABLED | SIR_TX_WITHOUT_ACREG2 | @@ -3265,7 +3265,7 @@ * FIFO configuration. * EFR[4] = 1 to allow to program FCR[5:4] and MCR[7:5]. */ - + WRITE_UART_REGISTER (uart, LCR, 0xBF); SET_BIT (uart, EFR, ENHANCED_FEATURE_BIT); @@ -3280,7 +3280,7 @@ mcr_value = DLAB; if (bpc == bpc_7) { - + mcr_value |= WLS_7; uart->bits_per_char += 7; @@ -3329,7 +3329,7 @@ * Program the trigger levels. * MCR[6] must be set to 1. */ - + SET_BIT (uart, MCR, TCR_TLR_BIT); WRITE_UART_REGISTER (uart, TCR, 0x0F); WRITE_UART_REGISTER (uart, TLR, RX_FIFO_TRIGGER_LEVEL); @@ -3341,7 +3341,7 @@ WRITE_UART_REGISTER ( uart, SCR, READ_UART_REGISTER (uart, SCR) | TX_EMPTY_CTL_IT); - + /* * Program the FIFO control register. Bit 0 must be set when other FCR bits * are written to or they are not programmed. @@ -3368,7 +3368,7 @@ /* * Select UART mode. */ - + WRITE_UART_REGISTER (uart, MDR1, ((baudrate==FD_BAUD_AUTO)? UART_MODE_AUTOBAUDING: UART_MODE) | @@ -3391,17 +3391,17 @@ /* * Read the state of DTR and select the edge. */ - + #ifdef CONFIG_TANGO_MODEM if (AI_Tango_pinmux[1] & 0x80) { #endif uart->dtr_level = AI_ReadBit (ARMIO_DTR); - + if (uart->dtr_level) AI_SelectIOForIT (ARMIO_DTR, ARMIO_FALLING_EDGE); else AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE); - + AI_UnmaskIT (ARMIO_MASKIT_GPIO); #ifdef CONFIG_TANGO_MODEM } else @@ -3422,13 +3422,13 @@ #if ((CHIPSET == 5) || (CHIPSET == 6)) /* - * Unmask RX and TX interrupts and the modem status interrupt. + * Unmask RX and TX interrupts and the modem status interrupt. */ WRITE_UART_REGISTER (uart, IER, ERBI | ETBEI | EDSSI); #elif (CHIPSET == 12) /* - * Unmask RX and TX interrupts and the modem status interrupt... + * Unmask RX and TX interrupts and the modem status interrupt... */ WRITE_UART_REGISTER (uart, IER, ERBI | ETBEI | EDSSI); @@ -3437,7 +3437,7 @@ * ... Then, unmask DSR interrupt... */ - ENABLE_DSR_INTERRUPT (uart); + ENABLE_DSR_INTERRUPT (uart); /* * ... And finally allow sleep mode. @@ -3449,7 +3449,7 @@ */ #else /* - * Unmask RX and TX interrupts and the modem status interrupt + * Unmask RX and TX interrupts and the modem status interrupt * and allow sleep mode. */ /* BELOW LINES WERE COMMENTED TO DISABLE SLEEP MODE IN DRIVER */ @@ -3466,7 +3466,7 @@ /******************************************************************************* * * UAF_SetBuffer - * + * * Purpose : Sets up the size of the circular buffers to be used in the UART * driver. This function may be called only if the UART is disabled * with UAF_Enable. @@ -3520,9 +3520,9 @@ result = FD_NOT_SUPPORTED; else { - + uart = &uart_parameters; - + if (!DRIVER_DISABLED (uart)) result = FD_INTERNAL_ERR; @@ -3530,7 +3530,7 @@ result = FD_NOT_SUPPORTED; else { - + uart->buffer_size = bufSize; uart->rx_threshold_level = rxThreshold; uart->tx_threshold_level = txThreshold; @@ -3545,7 +3545,7 @@ /******************************************************************************* * * UAF_SetFlowCtrl - * + * * Purpose : Changes the flow control mode of the UART driver. * If a flow control is activated, DTR is activated or XOFF is sent * if the RX buffer is not able to store the received characters else @@ -3594,12 +3594,12 @@ result = FD_NOT_SUPPORTED; else { - + uart = &uart_parameters; uart->tx_stopped_by_driver = 0; - + uart->xon_character = XON; uart->xoff_character = XOFF; uart->flow_control_mode = fcMode; @@ -3615,7 +3615,7 @@ WRITE_UART_REGISTER ( uart, MCR, READ_UART_REGISTER (uart, MCR) | MRTS); - + #if ((CHIPSET != 5) && (CHIPSET != 6)) /* * Re-enable sleep mode. @@ -3690,9 +3690,9 @@ uart->rx_stopped_by_driver = 0; start_receiver (uart); } - + } else { - + uart->rx_stopped_by_driver = 0; uart->tx_stopped_by_driver = 0; } @@ -3706,7 +3706,7 @@ /******************************************************************************* * * UAF_SetEscape - * + * * Purpose : To return to the command mode at the ACI while a data connection * is established, an escape sequence has to be detected. * To distinguish between user data and the escape sequence a @@ -3764,7 +3764,7 @@ /******************************************************************************* * * UAF_InpAvail - * + * * Purpose : Returns the number of characters available in the RX buffer of the * driver. If the driver is disabled the function returns 0. * @@ -3862,7 +3862,7 @@ /******************************************************************************* * * UAF_OutpAvail - * + * * Purpose : Returns the number of free characters in TX buffer of the driver. * If the driver is disabled the function returns 0. * @@ -3942,7 +3942,7 @@ /* * Disable sleep mode. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); #endif @@ -3950,7 +3950,7 @@ /* * Unmask Tx interrupt. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI); } @@ -3965,7 +3965,7 @@ /******************************************************************************* * * UAF_EnterSleep - * + * * Purpose : Checks if UART is ready to enter Deep Sleep. If ready, enables * wake-up interrupt. * @@ -3986,7 +3986,7 @@ t_uart *uart; SYS_BOOL deep_sleep; volatile SYS_UWORD8 status; - + /* * Check UART number. * A return is used to simplify the code. @@ -4015,7 +4015,7 @@ /* * Disable sleep mode. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); #endif @@ -4051,7 +4051,7 @@ /******************************************************************************* * * UAF_WakeUp - * + * * Purpose : Wakes up UART after Deep Sleep. * * Arguments: In : uartNo: Used UART. @@ -4068,7 +4068,7 @@ UAF_WakeUp (T_fd_UartId uartNo) { t_uart *uart; - + /* * Check UART number. * A return is used to simplify the code. @@ -4108,9 +4108,9 @@ /* * Allow sleep mode. */ - /* BELOW LINES WERE COMMENTED TO DISABLE SLEEP MODE IN DRIVER */ + /* BELOW LINES WERE COMMENTED TO DISABLE SLEEP MODE IN DRIVER */ /* - WRITE_UART_REGISTER ( + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP); */ #endif @@ -4121,7 +4121,7 @@ /******************************************************************************* * * UAF_ReadData - * + * * Purpose : To read the received characters out of the RX buffer the address * of a function is passed. If characters are available, the driver * calls this function and pass the address and the amount of @@ -4168,7 +4168,7 @@ * size : Array which contains the sizes of * each fragments. * state : The state parameter is the status - * of the V.24 lines and the break / + * of the V.24 lines and the break / * escape detection. The state * parameter is described in the * specification of UAF_GetLineState. @@ -4260,11 +4260,11 @@ result = FD_SUSPENDED; } else { - + /* * The previous callback function is deinstalled. */ - + uart->rd_call_setup = rm_noInstall; uart->reading_suspended = 0; result = 0; /* 0 byte read. */ @@ -4276,7 +4276,7 @@ /******************************************************************************* * * UAF_WriteData - * + * * Purpose : To write characters into the TX buffer the address of a function * is passed. If free space is available in the buffer, the driver * calls this function and passes the destination address and the @@ -4298,7 +4298,7 @@ * * Arguments: In : uartNo : Used UART. * suspend : mode of suspension in case of TX buffer empty. - * writeInFunc: Callback function. + * writeInFunc: Callback function. * cldFromIrq: The driver sets this parameter to 1 * if the call-back function is called * from an interrupt service routine. @@ -4397,12 +4397,12 @@ */ if (!uart->break_to_send && !uart->tx_stopped_by_driver) - { + { #if ((CHIPSET != 5) && (CHIPSET != 6)) /* * Disable sleep mode. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP); #endif @@ -4410,7 +4410,7 @@ /* * Unmask Tx interrupt. */ - + WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI); } @@ -4424,11 +4424,11 @@ result = FD_SUSPENDED; } else { - + /* * The previous callback function is deinstalled. */ - + uart->wr_call_setup = rm_noInstall; uart->writing_suspended = 0; result = 0; @@ -4440,7 +4440,7 @@ /******************************************************************************* * * UAF_StopRec - * + * * Purpose : If a flow control mode is set, this function tells the terminal * equipment that no more data can be received. * XON/XOFF: XOFF is sent. @@ -4490,7 +4490,7 @@ /******************************************************************************* * * UAF_StartRec - * + * * Purpose : If a flow control mode is set, this function tells the terminal * equipment that the receiver is again able to receive more data. * If the buffer has already reached the high water mark the driver @@ -4508,7 +4508,7 @@ * ******************************************************************************/ -T_FDRET +T_FDRET UAF_StartRec (T_fd_UartId uartNo) { t_uart *uart; @@ -4542,7 +4542,7 @@ /******************************************************************************* * * UAF_GetLineState - * + * * Purpose : Returns the state of the V.24 lines, the flow control state and * the result of the break/escape detection process as a bit field. * @@ -4553,7 +4553,7 @@ * * Returns : FD_OK : Successful operation. * FD_NOT_SUPPORTED: Wrong UART number. - * FD_NOT_READY : The function is called while the callback of + * FD_NOT_READY : The function is called while the callback of * the readOutFunc function is activated and still * not terminated. * FD_INTERNAL_ERR : Internal problem with the hardware. @@ -4595,7 +4595,7 @@ * The field state_2 is used when state_1 is set to 0 to avoid to * lose events detected in the RX interrupt handler. * Fields BRK and BRKLEN are set when a break is detected. - * The field ESC is set when an escape sequence is detected. + * The field ESC is set when an escape sequence is detected. */ *state = uart->state_2; @@ -4607,7 +4607,7 @@ uart->state = &(uart->state_1); *state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | - + #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12)) (((SYS_UWORD32) uart->dtr_level) << DTR) | #endif @@ -4618,9 +4618,9 @@ (((SYS_UWORD32) (uart->rx_stopped_by_application | uart->rx_stopped_by_driver)) << RXSTP) | - (((SYS_UWORD32) (uart->buffer_size - + (((SYS_UWORD32) (uart->buffer_size - get_bytes_in_rx_buffer (uart))) << RXBLEV)); - + /* * Fields SA, SB and X are set according to the flow control: * @@ -4641,7 +4641,7 @@ if (uart->flow_control_mode == fc_rts) *state |= (((SYS_UWORD32) uart->rts_level) << X); - + else if ((uart->flow_control_mode == fc_xoff) && (uart->tx_stopped_by_application || uart->tx_stopped_by_driver)) @@ -4656,7 +4656,7 @@ /******************************************************************************* * * UAF_SetLineState - * + * * Purpose : Sets the states of the V.24 status lines according to the bit * field of the parameter state. * @@ -4709,7 +4709,7 @@ if ((mask & (1 << SA)) || (mask & (1 << DCD))) #endif return (FD_NOT_SUPPORTED); /* Return used to simplify the code */ - + /* * Check if a break has to be sent. */ @@ -4753,9 +4753,9 @@ */ if (mask & (1 << CTS)) { - + if (uart->flow_control_mode != fc_rts) { - + /* * As the RTS/CTS flow control is not selected, the X bit does not * control CTS. CTS needs only to be activated or deactivated @@ -4779,19 +4779,19 @@ * The receiver is started only if it was not stopped by the driver * and if it was stopped by the application. */ - + if (state & (1 << CTS)) { if (!uart->rx_stopped_by_application) { - + if (!uart->rx_stopped_by_driver) stop_receiver (uart); uart->rx_stopped_by_application = 1; } - + } else { - + if ((!uart->rx_stopped_by_driver) && uart->rx_stopped_by_application) start_receiver (uart); @@ -4891,21 +4891,36 @@ #endif /* Tango modem */ +#ifdef CONFIG_TARGET_GTM900 + + if (mask & (1 << RI)) { + + if (state & (1 << RI)) { + /* Turn on RI */ + AI_ResetBit(0); + } else { + /* Turn off RI */ + AI_SetBit(0); + } + } + +#endif /* GTM900 modem */ + if ((mask & (1 << X)) && (uart->flow_control_mode != fc_none)) { if (state & (1 << X)) { - + if (!uart->rx_stopped_by_application) { - + if (!uart->rx_stopped_by_driver) stop_receiver (uart); uart->rx_stopped_by_application = 1; } - + } else { - + /* * The receiver is started only if it is not stopped by the driver * and if it is stopped by the application. @@ -4923,7 +4938,7 @@ /* * Re-enable sleep mode. */ - /* BELOW LINES WERE COMMENTED TO DISABLE SLEEP MODE IN DRIVER */ + /* BELOW LINES WERE COMMENTED TO DISABLE SLEEP MODE IN DRIVER */ /* WRITE_UART_REGISTER ( uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP); @@ -4936,7 +4951,7 @@ /******************************************************************************* * * UAF_InterruptHandler - * + * * Purpose : Interrupt handler. * * Arguments: In : uart_id : origin of interrupt @@ -5051,7 +5066,7 @@ /******************************************************************************* * * UAF_CheckXEmpty - * + * * Purpose : Checks the empty condition of the Transmitter. * * Arguments: In : uartNo: Used UART. @@ -5088,7 +5103,7 @@ */ result = FD_OK; - + uart = &uart_parameters; status = READ_UART_REGISTER (uart, LSR); @@ -5129,16 +5144,16 @@ UAF_DTRInterruptHandler (void) { t_uart *uart; - + uart = &uart_parameters; - + /* * Read the state of DTR and change the edge to detect the next change * of DTR. */ - + uart->dtr_level = AI_ReadBit (ARMIO_DTR); - + if (uart->dtr_level) { AI_SelectIOForIT (ARMIO_DTR, ARMIO_FALLING_EDGE); @@ -5147,28 +5162,28 @@ } else AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE); - + /* * The reading callback function has to be called. But bytes received before * the change of state of DTR must be copied into the RX buffer before to * call it. */ - + if (READ_UART_REGISTER (uart, LSR) & DR) { /* If Rx FIFO is not empty */ - + /* * The Rx FIFO will be read to fill one of the two buffers and the Rx * HISR will be activated. */ - + uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */ uart->dtr_change_detected[uart->index_it] = 1; uart->dtr_level_saved[uart->index_it] = uart->dtr_level; read_rx_fifo (uart); - + } else (void) NU_Activate_HISR (&(uart->v24_hisr_ctrl_block)); - + } #endif /* BOARD 8 or 9 or 40 or 41 */ @@ -5176,8 +5191,8 @@ /******************************************************************************* * * UAF_Exit - * - * Purpose : + * + * Purpose : * * Arguments: In : uartNo: Used UART. * Out: none