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annotate fpga/sniffer-pps/pps_catcher.v @ 28:0f74428c177c

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fpga/sniffer-pps: first version
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 20:05:23 +0000
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children
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28
0f74428c177c fpga/sniffer-pps: first version
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
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Mychaela Falconia <falcon@freecalypso.org>
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2 * This Verilog module is our PPS catcher. It is a state machine that analyzes
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Mychaela Falconia <falcon@freecalypso.org>
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3 * the stream of Rx characters from the primary sniffer and detects the
0f74428c177c fpga/sniffer-pps: first version
Mychaela Falconia <falcon@freecalypso.org>
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4 * positions of these two special chars:
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Mychaela Falconia <falcon@freecalypso.org>
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5 *
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Mychaela Falconia <falcon@freecalypso.org>
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6 * - the PPS1 byte of the card's PPS response;
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7 * - the PCK byte concluding that PPS response *if* PPS1 indicated a speed
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Mychaela Falconia <falcon@freecalypso.org>
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8 * enhancement mode which we support.
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9 */
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10
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11 module pps_catcher (IntClk, SIM_RST_sync, Rx_strobe, Rx_char,
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12 pos_PPS_resp_PPS1, pos_PPS_resp_PCK);
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13
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14 input IntClk;
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Mychaela Falconia <falcon@freecalypso.org>
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15 input SIM_RST_sync;
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16 input Rx_strobe;
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17 input [7:0] Rx_char;
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18
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19 output pos_PPS_resp_PPS1, pos_PPS_resp_PCK;
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20
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21 /* state machine */
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22
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23 localparam
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24 INITIAL = 5'h00,
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25 ATR_T0 = 5'h01,
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26 ATR_TAn = 5'h02,
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27 ATR_TBn = 5'h03,
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28 ATR_TCn = 5'h04,
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29 ATR_TDn = 5'h05,
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30 ATR_HIST = 5'h06,
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31 ATR_TCK = 5'h07,
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32 READY_FOR_PPS = 5'h08,
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33 REQ_PPS0 = 5'h09,
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34 REQ_PPS1 = 5'h0A,
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35 REQ_PPS2 = 5'h0B,
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36 REQ_PPS3 = 5'h0C,
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37 REQ_PCK = 5'h0F,
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38 READY_FOR_RESP = 5'h10,
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39 RESP_PPS0 = 5'h11,
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40 RESP_PPS1 = 5'h12,
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41 RESP_PPS2 = 5'h13,
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42 RESP_PPS3 = 5'h14,
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43 RESP_PCK = 5'h17,
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44 DONE = 5'h1F
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45 ;
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46
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47 reg [4:0] state;
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48 reg [3:0] Y, K;
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49 reg have_TCK;
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50
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51 always @(posedge IntClk)
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52 if (!SIM_RST_sync)
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53 begin
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54 state <= INITIAL;
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55 have_TCK <= 1'b0;
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56 end
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57 else case (state)
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58 INITIAL:
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59 if (Rx_strobe)
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60 begin
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61 if (Rx_char == 8'h3B)
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62 state <= ATR_T0;
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63 else
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64 state <= DONE;
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65 end
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66 ATR_T0:
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67 if (Rx_strobe)
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68 begin
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69 Y <= Rx_char[7:4];
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70 K <= Rx_char[3:0];
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71 state <= ATR_TAn;
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72 end
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73 ATR_TAn:
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74 if (!Y[0] || Rx_strobe)
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75 state <= ATR_TBn;
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76 ATR_TBn:
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77 if (!Y[1] || Rx_strobe)
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78 state <= ATR_TCn;
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79 ATR_TCn:
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80 if (!Y[2] || Rx_strobe)
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81 state <= ATR_TDn;
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82 ATR_TDn:
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83 if (!Y[3])
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84 state <= ATR_HIST;
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85 else if (Rx_strobe)
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86 begin
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87 Y <= Rx_char[7:4];
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88 if (Rx_char[3:0] != 4'h0)
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89 have_TCK <= 1'b1;
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90 state <= ATR_TAn;
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91 end
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92 ATR_HIST:
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93 if (K == 4'd0)
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94 state <= ATR_TCK;
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95 else if (Rx_strobe)
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96 K <= K - 4'd1;
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97 ATR_TCK:
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98 if (!have_TCK || Rx_strobe)
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99 state <= READY_FOR_PPS;
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100 READY_FOR_PPS:
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101 if (Rx_strobe)
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102 begin
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103 if (Rx_char == 8'hFF)
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104 state <= REQ_PPS0;
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105 else
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106 state <= DONE;
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107 end
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108 REQ_PPS0:
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109 if (Rx_strobe)
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110 begin
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111 Y <= Rx_char[7:4];
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112 state <= REQ_PPS1;
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113 end
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114 REQ_PPS1:
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115 if (!Y[0] || Rx_strobe)
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116 state <= REQ_PPS2;
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117 REQ_PPS2:
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118 if (!Y[1] || Rx_strobe)
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119 state <= REQ_PPS3;
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120 REQ_PPS3:
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121 if (!Y[2] || Rx_strobe)
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122 state <= REQ_PCK;
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123 REQ_PCK:
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124 if (Rx_strobe)
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125 state <= READY_FOR_RESP;
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126 READY_FOR_RESP:
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127 if (Rx_strobe)
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128 begin
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129 if (Rx_char == 8'hFF)
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130 state <= RESP_PPS0;
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131 else
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132 state <= DONE;
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133 end
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134 RESP_PPS0:
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135 if (Rx_strobe)
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136 begin
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137 Y <= Rx_char[7:4];
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138 if (Rx_char[4])
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139 state <= RESP_PPS1;
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140 else
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141 state <= DONE;
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142 end
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143 RESP_PPS1:
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144 if (Rx_strobe)
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145 begin
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146 if (Rx_char[7:2] == 6'b100101)
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147 state <= RESP_PPS2;
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148 else
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149 state <= DONE;
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150 end
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151 RESP_PPS2:
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152 if (!Y[1] || Rx_strobe)
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153 state <= RESP_PPS3;
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154 RESP_PPS3:
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155 if (!Y[2] || Rx_strobe)
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156 state <= RESP_PCK;
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157 RESP_PCK:
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158 if (Rx_strobe)
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parents:
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159 state <= DONE;
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parents:
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160 endcase
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parents:
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161
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162 assign pos_PPS_resp_PPS1 = (state == RESP_PPS1);
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163 assign pos_PPS_resp_PCK = (state == RESP_PCK);
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parents:
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164
0f74428c177c fpga/sniffer-pps: first version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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165 endmodule