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doc: describe proposed FPGA design
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 29 Jul 2023 07:06:54 +0000
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children 41e6026e5d1a
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1 The first FPGA gateware function to be implemented in the SIMtrace-ice project
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2 is the passive sniffer: receiving level-shifted SIM RST, CLK and I/O signals
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3 from the 74LVC4T3144 buffer and capturing all exchanges that happen on the SIM
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4 interface between a DUS and a SIM.
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5
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6 The sniffer FPGA logic function will be implemented on the inexpensive off-the-
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7 shelf Icestick board, featuring an iCE40HX1K FPGA and an FT2232H-based USB host
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8 interface. This FPGA logic function will operate principally as a byte
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9 forwarder from the ISO 7816-3 sniffer block to the FT2232H UART: every time the
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10 bus sniffer block captures a character (in ISO 7816-3 terminology) being passed
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11 on the SIM electrical interface in either direction (the two directions of
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12 transmission are indistinguishable to a tap sniffer that does not actively
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13 participate in the protocol), the FPGA will forward this character to the
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14 connected host computer (by way of FT2232H UART) for further processing in
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15 software. The UART data line going from the FPGA to the FT2232H will be the
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16 sole functional output from this FPGA, beyond debug outputs being added during
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17 logic development and troubleshooting. The other UART data line going the
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18 opposite direction (output from FT2232H) will remain unused, i.e., the host
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19 software application will only read/receive from the ttyUSBx FPGA device and
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20 won't send anything to it. All modem control lines on this UART interface will
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21 likewise remain unused.
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22
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23 Serial interface format
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24 =======================
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25
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26 For every ISO 7816-3 character captured by the sniffer, two back-to-back UART
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27 bytes will be transferred from the FPGA to the host computer; more generally,
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28 the FPGA will only transmit pairs of back-to-back bytes on this UART and no
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29 singletons or other arrangements - thus the host receiver can always recover
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30 synchronization by dropping any partially received two-byte message (the first
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31 byte of an expected pair) during prolonged pauses. The FPGA will transmit the
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32 two back-to-back UART bytes as a single shift-out of 20 bits, conveying two
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33 bytes in 8N1 framing.
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34
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35 Why are we turning every captured ISO 7816-3 character into a pair of bytes on
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36 our internal UART interface, why not simply forward it as a single byte? The
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37 reason is that we need to pass some additional bits beyond the 8 that comprise
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38 the ISO 7816-3 character payload; the additional bits which we need to pass are
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39 as follows:
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40
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41 - the received parity bit;
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42 - a flag indicating whether or not an error signal (ISO 7816-3 section 7.3)
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43 was seen;
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44 - additional flag bits communicating SIM RST assertion and negation events,
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45 as distinct from ISO 7816-3 characters;
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46 - an additional flag indicating an action of the integrated PPS catcher state
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47 machine, to be described later in this document.
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48
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49 Assertion or negation of SIM RST is the only other possible event (besides ISO
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50 7816-3 character capture, with or without attendant PPS catcher state machine
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51 action) that can cause the FPGA to send a byte-pair UART message to the host
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52 computer. One bit in the 16-bit message will distinguish between characters
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53 and RST events, another bit will indicate the state of RST at the time of the
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54 event (new RST for transitions, 1 for characters), and all other bits are
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55 meaningful only for characters.
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56
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57 Clocking design
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58 ===============
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59
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60 The FPGA on the Icestick board receives a 12 MHz clock input; the on-chip PLL
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61 will be used to multiply this clock by 4, producing a 48 MHz system clock.
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62 This 48 MHz SYSCLK will be used for the entirety of the present logic design -
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63 a single-clock fully synchronous design is the best current practice.
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64
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65 The 3 inputs to the FPGA coming from the SIM electrical sniffer (buffered and
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66 level-shifted SIM RST, CLK and I/O lines) will pass through two cascaded DFFs,
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67 bringing them into our internal clock domain. The delay added by these cascaded
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68 DFFs is not a concern: we are a passive sniffer without any output back to the
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69 SIM interface, and all 3 signal inputs will be subject to the same delay.
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70
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71 The baud rate on the UART interface between the FPGA and the FT2232H converter
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72 will be 3000000 bps. The UART output block in the FPGA will use a simple /16
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73 divider from SYSCLK to time its output bits; future derivative designs that will
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74 use the UART interface bidirectionally (such as the planned card emulator FPGA
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75 design) will use SYSCLK directly as the 16x clock for UART reception. This
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76 high (and very non-RS232-standard) UART baud rate was chosen for the following
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77 reasons:
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78
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79 * Our UART interface is totally private, going nowhere but the on-board FT2232H,
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80 thus it doesn't matter if the baud rate is standard-ish or totally
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81 non-standard.
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82
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83 * No cables of any kind are used, instead the UART interface is confined to
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84 short PCB traces running between the FPGA and the FTDI chip on the same board
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85 - hence high baud rates are not a problem.
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86
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87 * Our UART baud rate needs to be high enough to provide good margin, despite
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88 our 2x expansion, at the highest possible effective bps rate on the SIM
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89 interface, meaning the highest possible SIM CLK frequency and the most
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90 aggressive F/D ratio. The combination of SIM CLK at 5 MHz, F=512 and D=64
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91 corresponds to 625000 bps effective on the SIM interface; running our UART at
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92 3 Mbps provides sufficient margin.
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93
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94 ISO 7816-3 sniffer block
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95 ========================
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96
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97 Our ISO 7816-3 receiver will trigger on the falling edge of the I/O line. Once
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98 it detects a high-to-low transition on the SYSCLK-synchronized SIM_IO input, it
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99 will start counting SIM CLK cycles - we are arbitrarily choosing low-to-high
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100 transition of SYSCLK-synchronized SIM_CLK input as the trigger point. (This
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101 choice is arbitrary because per the spec there is no defined phase relation
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102 between SIM CLK and SIM I/O transitions.) Our ISO 7816-3 receiver will need to
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103 know how many SIM CLK cycles constitute one etu - or more precisely, our
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104 sniffing receiver will operate in half-etu counts, as we need to measure 0.5 etu
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105 to get from the initial falling edge on the I/O line to the mid-etu data
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106 sampling point. Following the session-opening low-to-high transition on the RST
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107 line, our half-etu register will be set to 8'd186, corresponding to F/D=372.
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108 Our PPS catcher state machine will then overwrite this register with a smaller
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109 value based on the captured PPS exchange.
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110
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111 Direct and inverse coding conventions
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112 =====================================
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113
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114 Only the card and not the DUS (interface device in ISO 7816-3 terminology)
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115 determines which coding convention is used, direct or inverse. So far we
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116 (FreeCalypso) have not yet encountered a real-life SIM that uses the inverse
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117 convention, only the direct convention kind. In the sniffer function of
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118 SIMtrace-ice, we are going to keep our FPGA gateware simple in this regard and
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119 punt all inverse convention handling to the software application on the host
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120 computer: the FPGA will pass the 9 received bits (8 data bits and 1 parity bit)
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121 to the 16-bit UART message as-is, without inverting or reordering them.
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122
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123 Integrated PPS catcher
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124 ======================
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125
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126 The logic described so far will be sufficient to capture all exchanges on the
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127 SIM interface between a DUS and a SIM *if* the etu-defining F/D ratio is never
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128 switched from the basic default of 372. However, given that most SIM cards of
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129 interest to us (our own FCSIM1, as well as SIMs issued by various commercial
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130 operators) support Fi=512 Di=8 or higher, and given that even very classic
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131 implementations of GSM ME (including our dear Calypso) support this F=512 D=8
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132 speed enhancement mode endorsed by GSM 11.11 spec, many real-life DUS-to-SIM
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133 sessions (which we would like to sniff and trace) will include a PPS exchange
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134 switching to a smaller number of SIM CLK cycles per etu.
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135
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136 The main difficulty with capturing SIM interface sessions that use speed
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137 enhancement is as follows: in order for the session capture to be complete,
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138 without any lost bits, the sniffing receiver's knowledge of how many SIM CLK
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139 cycles constitute a half-etu needs to change to the new value at exactly the
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140 correct moment in time, which is the moment immediately after the last byte
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141 (PCK) of the SIM's PPS response passes across the wire. If we were to rely on
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142 host software to decode all byte exchanges up to this point (ATR from the SIM,
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143 PPS request from the DUS, then PPS response) and command the FPGA (UART in the
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144 other direction, or a modem control line) to switch the half-etu counter, we
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145 stand very little chance of getting this command to the FPGA in time, before
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146 the DUS starts transmitting its next command to the SIM using the new etu
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147 definition.
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148
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149 The Mother's proposed solution is to embed a PPS catcher state machine in the
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150 sniffer FPGA. This state machine will be set to its initial state upon the
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151 session-opening low-to-high transition on the RST line, and it will look at
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152 every ISO 7816-3 character received by the sniffer. The machine will need to
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153 step through the following states between this starting point and the final
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154 action of changing the half-etu count register:
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155
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156 * As the ATR bytes are transferred, the state machine will need to understand
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157 enough of ATR format to know which byte constitutes the end of ATR. A fatal
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158 error in ATR real-time parsing (if the first byte is anything other than
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159 8'h3B) will put the machine into its inactive state for the remainder of the
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160 session until next reset.
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161
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162 * If the byte following ATR is 8'hFF, the machine will proceed into PPS request
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163 real-time parsing state. If this byte equals any other value, go to the
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164 inactive state for the remainder of the session.
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165
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166 * In the PPS request real-time parsing series of states, the state machine will
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167 need to catch the PPS0 byte and based on this byte, figure out how many bytes
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168 it needs to skip.
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169
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170 * Following the PPS request, the machine will need to real-time-parse the PPS
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171 response. Any invalid conditions will take it to the inactive state; however,
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172 if the PPS exchange is valid, the machine will need to capture the PPS1 byte
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173 and then step through states until the final PCK byte of the PPS response.
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174
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175 * Upon receiving that last PCK byte after all prior bytes following the expected
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176 protocol, effect the half-etu count change. Either way, the inactive state
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177 is entered at this point, and the state machine will take no further action
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178 for the remainder of the session.
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179
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180 This state machine is of course going to be very complicated, as evident from
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181 the functional requirements listed above. The first version of SIMtrace-ice
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182 sniffer FPGA will omit this block altogether, and we will get the rest of the
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183 system working for DUS-to-SIM sessions that stick with F/D=372 - a good test
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184 configuration would be to use a FreeCalypso GSM ME as DUS, with SIM speed
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185 enhancement disabled via AT@SPENH=0. Then we shall embark on implementing this
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186 proposed PPS catcher state machine.
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187
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188 The addition of this PPS catcher state machine may increase the complexity of
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189 our logic beyond the capacity of the iCE40HX1K FPGA on the Icestick board. If
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190 we run into this problem, we'll have to look for a board with a bigger FPGA -
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191 but we'll try to fit into the Icestick first.