FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-basic/clk_edge.v @ 25:c03a882cc49e

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
doc/Sniffer-FPGA-design: update for working status
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 06:37:58 +0000
parents 7db5fd6646df
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /*
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * This Verilog module captures the logic that detects rising edges of SIM_CLK
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 * for the purpose of counting them.
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 */
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 module clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge);
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 input IntClk;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 input SIM_CLK_sync;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 output SIM_CLK_edge;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 reg prev_state;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 always @(posedge IntClk)
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 prev_state <= SIM_CLK_sync;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 assign SIM_CLK_edge = SIM_CLK_sync && !prev_state;
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 endmodule