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comparison fpga/sniffer-pps/clk_edge.v @ 28:0f74428c177c

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fpga/sniffer-pps: first version
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 20:05:23 +0000
parents fpga/sniffer-basic/clk_edge.v@7db5fd6646df
children
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27:990ecafdddb4 28:0f74428c177c
1 /*
2 * This Verilog module captures the logic that detects rising edges of SIM_CLK
3 * for the purpose of counting them.
4 */
5
6 module clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge);
7
8 input IntClk;
9 input SIM_CLK_sync;
10 output SIM_CLK_edge;
11
12 reg prev_state;
13
14 always @(posedge IntClk)
15 prev_state <= SIM_CLK_sync;
16
17 assign SIM_CLK_edge = SIM_CLK_sync && !prev_state;
18
19 endmodule