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comparison fpga/sniffer-basic/clk_edge.v @ 6:7db5fd6646df

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fpga/sniffer-basic: initial version
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 00:52:00 +0000
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5:07c5aac6e84f 6:7db5fd6646df
1 /*
2 * This Verilog module captures the logic that detects rising edges of SIM_CLK
3 * for the purpose of counting them.
4 */
5
6 module clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge);
7
8 input IntClk;
9 input SIM_CLK_sync;
10 output SIM_CLK_edge;
11
12 reg prev_state;
13
14 always @(posedge IntClk)
15 prev_state <= SIM_CLK_sync;
16
17 assign SIM_CLK_edge = SIM_CLK_sync && !prev_state;
18
19 endmodule