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comparison fpga/sniffer-pps/spenh_ctrl.v @ 31:ab37fcb71744

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fpga/sniffer-pps: add actual F/D control
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 21:22:37 +0000
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30:dc99c9962aed 31:ab37fcb71744
1 /*
2 * This module implements speed enhancement control based on signals
3 * from the PPS catcher block.
4 */
5
6 module spenh_ctrl (IntClk, SIM_RST_sync, Rx_strobe, Rx_char,
7 pos_PPS_resp_PPS1, pos_PPS_resp_PCK,
8 speed_enh_mode, speed_enh_mult);
9
10 input IntClk;
11 input SIM_RST_sync;
12 input Rx_strobe;
13 input [7:0] Rx_char;
14 input pos_PPS_resp_PPS1, pos_PPS_resp_PCK;
15
16 output reg speed_enh_mode;
17 output reg [1:0] speed_enh_mult;
18
19 always @(posedge IntClk)
20 if (!SIM_RST_sync)
21 speed_enh_mode <= 1'b0;
22 else if (Rx_strobe && pos_PPS_resp_PCK)
23 speed_enh_mode <= 1'b1;
24
25 always @(posedge IntClk)
26 if (Rx_strobe && pos_PPS_resp_PPS1)
27 speed_enh_mult <= Rx_char[1:0];
28
29 endmodule