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+++ b/doc/Cardem-plans	Wed Aug 30 03:32:06 2023 +0000
@@ -0,0 +1,42 @@
+The long-term goal of SIMtrace3 project is to support both SIM interface
+sniffing and card emulation.  Both functions are needed when working in the
+realm of Vintage Mobile Phones:
+
+* Non-invasive, Heisenbug-free Hi-Z sniffing is needed in order to see why
+  certain phone-to-SIM combinations work while others don't, and to see exactly
+  what a given finicky phone requires from that special hard-to-get SIM.
+
+* The next step of cloning that special SIM, or producing new SIMs that satisfy
+  the weird requirements of the finicky phone, will often require full emulation
+  of ISO 7816-4 / GSM 11.11 file system and CardOS in software, as we don't have
+  a real smartcard chip that gives us full freedom to implement whatever we
+  like.
+
+However, in terms of scheduling priority, all of our initial work focuses on
+the sniffer, with cardem deferred to some indefinite later time.  We do,
+however, have a preliminary idea of how we envision cardem working:
+
+* Hardware setups will be different between sniffing and cardem.  Our initial
+  objective is to produce a solidly usable, production quality sniffer pod,
+  described as HW setup version 2 in the Sniffing-hw-setup article.  As the
+  name says, this pod will be for sniffing only.  For card emulation there will
+  be a different cardem pod.
+
+* The cardem pod will be similar to the sniffer pod, with just two changes:
+
+  - We'll add a 74LVC1G07 OD driver for pulling the I/O line low in exactly the
+    same way how real SIM cards do it;
+
+  - The SIM socket will be eliminated from the cardem pod, to eliminate any
+    possibility of a real SIM and cardem "fighting" to talk back to the same
+    ME/ID.
+
+* FPGA gateware will also be different between sniffing and cardem.  The cardem
+  design is expected to be more complex and use more FPGA resources, but there
+  is a good chance it will still fit into iCE40-HX1K FPGA and thus allow us to
+  keep using the same Icestick board.
+
+* Right now we have no plans to stick a soft CPU core into the FPGA for cardem,
+  instead the plan is to use the same principal architecture as the sniffer
+  FPGA, using the UART channel at 3 Mbps to communicate with the host - although
+  this time this UART will be used bidirectionally.