FreeCalypso > hg > fc-sim-sniff
view fpga/sniffer-basic/clk_edge.v @ 49:7e87b03dd57d
doc/Sniffing-workflow: document simsniff-dec
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 21 Sep 2023 06:47:03 +0000 |
parents | 7db5fd6646df |
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/* * This Verilog module captures the logic that detects rising edges of SIM_CLK * for the purpose of counting them. */ module clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge); input IntClk; input SIM_CLK_sync; output SIM_CLK_edge; reg prev_state; always @(posedge IntClk) prev_state <= SIM_CLK_sync; assign SIM_CLK_edge = SIM_CLK_sync && !prev_state; endmodule