FreeCalypso > hg > fc-sim-sniff
view sw/sniff-rx/byteproc.c @ 31:ab37fcb71744
fpga/sniffer-pps: add actual F/D control
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 29 Aug 2023 21:22:37 +0000 |
parents | b112c2df6c43 |
children | 43f678895a3a |
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/* * In this module we implement byte-level processing of the serial stream * coming from the sniffer FPGA. */ #include <sys/time.h> #include <stdio.h> #include <stdlib.h> #include <time.h> extern FILE *main_outf; extern int logfile_flag; extern struct timeval curtime; extern struct tm *cur_tm; static int byte_pending_flag, byte_pending_val; void rx_byte_in(new_byte) { if (!byte_pending_flag) { byte_pending_flag = 1; byte_pending_val = new_byte; return; } /* received complete 2-byte message from the FPGA */ fprintf(main_outf, "[%02d:%02d:%02d.%06u] %02X%02X\n", cur_tm->tm_hour, cur_tm->tm_min, cur_tm->tm_sec, (unsigned) curtime.tv_usec, new_byte, byte_pending_val); byte_pending_flag = 0; if (logfile_flag && (new_byte & 0x80)) printf("SIM RST is %s\n", new_byte & 0x40 ? "high" : "low"); } void flush_pending_byte() { if (!byte_pending_flag) return; printf("BAD BAD BAD: loss of byte sync with FPGA source!\n"); byte_pending_flag = 0; }