FreeCalypso > hg > fc-sim-sniff
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doc: on later thought, drop the DUS term in favor of ME/ID20 months ago, by Mychaela Falconia
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FPGA make clean: rm *.rpt too20 months ago, by Mychaela Falconia
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FPGA build: include yosys-wrap in this repository20 months ago, by Mychaela Falconia
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doc/Sniffer-FPGA-design: update for first implementation20 months ago, by Mychaela Falconia
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.hgignore: add mv-sniffer gerber files20 months ago, by Mychaela Falconia
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boards/mv-sniffer/pcb: add Makefile20 months ago, by Mychaela Falconia
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boards/mv-sniffer: PCB layout done20 months ago, by Mychaela Falconia
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FPGA Makefile: generate timing.rpt20 months ago, by Mychaela Falconia
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FPGA Makefile: generate pnr.rpt20 months ago, by Mychaela Falconia
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fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED20 months ago, by Mychaela Falconia
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fpga/sniffer-basic/sniff_rx.v: typo in signal name20 months ago, by Mychaela Falconia
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FPGA Makefile: capture yosys stdout20 months ago, by Mychaela Falconia