FreeCalypso > hg > fc-small-hw
annotate lunalcd2/src/vsrc/bl_current_sink.v @ 71:31c8b1291b4a
lunalcd3 project started
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 18 Nov 2021 04:59:47 +0000 |
parents | d5d14b426faa |
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rev | line source |
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59
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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1 module bl_current_sink (GND, Vio, BL_EN, LEDK); |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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2 |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 input GND, Vio, BL_EN; |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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4 output [1:3] LEDK; |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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5 |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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6 wire SET; |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 MAX1916 MAX1916 (.GND(GND), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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9 .EN(BL_EN), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 .SET(SET), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 .LEDK(LEDK) |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 ); |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 current_select cursel ( .Vio(Vio), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 .SET(SET) |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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16 ); |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
17 |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
18 endmodule |