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view lunalcd2/src/vsrc/bl_current_sink.v @ 84:dbd57e8dd82a default tip

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sim-fpc-pasv/pcb: add Makefile for Gerber output
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 02 Nov 2022 07:22:44 +0000
parents d5d14b426faa
children
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module bl_current_sink (GND, Vio, BL_EN, LEDK);

input GND, Vio, BL_EN;
output [1:3] LEDK;

wire SET;

MAX1916 MAX1916 (.GND(GND),
		 .EN(BL_EN),
		 .SET(SET),
		 .LEDK(LEDK)
	);

current_select cursel ( .Vio(Vio),
			.SET(SET)
	);

endmodule