FreeCalypso > hg > fc-small-hw

annotate lunalcd2/src/Makefile @ 60:38c713964bb7

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
lunalcd2: MCL binding complete
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 19:01:35 +0000
parents d5d14b426faa
children df8f40386c0b
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
59
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 VSRCS= vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 vsrc/current_select.v vsrc/lcd_module.v
60
38c713964bb7 lunalcd2: MCL binding complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 59
diff changeset
3 NETS= sverp.unet bound.unet
59
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 all: ${NETS}
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 sverp.unet: ${VSRCS} primitives Makefile
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 ueda-sverp -o $@ ${VSRCS}
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9
60
38c713964bb7 lunalcd2: MCL binding complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 59
diff changeset
10 bound.unet: MCL sverp.unet
38c713964bb7 lunalcd2: MCL binding complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 59
diff changeset
11 unet-bind -c sverp.unet $@
38c713964bb7 lunalcd2: MCL binding complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 59
diff changeset
12
59
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 clean:
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 rm -f *.unet *.txt *.csv errs elements.pcb