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annotate lunalcd2/src/vsrc/lcd_module.v @ 60:38c713964bb7

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lunalcd2: MCL binding complete
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 19:01:35 +0000
parents d5d14b426faa
children
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d5d14b426faa lunalcd2: structural Verilog source captured
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1 module lcd_module (GND, VCI, IOVCC, DB, RD, WR, RS, CS, RESET, IM0, LEDA, LEDK);
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2
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3 input GND, VCI, IOVCC;
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4 inout [15:0] DB;
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5 input RD, WR, RS, CS, RESET, IM0;
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6 input LEDA;
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7 input [1:3] LEDK;
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8
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9 /* instantiate the package; the mapping of signals to pins is defined here */
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10
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11 lcd_module_fp pkg (.pin_1(DB[15]),
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12 .pin_2(DB[14]),
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13 .pin_3(DB[13]),
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14 .pin_4(DB[12]),
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15 .pin_5(DB[11]),
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16 .pin_6(DB[10]),
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17 .pin_7(DB[9]),
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18 .pin_8(DB[8]),
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19 .pin_9(GND),
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20 .pin_10(DB[7]),
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21 .pin_11(DB[6]),
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22 .pin_12(DB[5]),
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23 .pin_13(DB[4]),
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24 .pin_14(DB[3]),
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25 .pin_15(DB[2]),
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26 .pin_16(DB[1]),
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27 .pin_17(DB[0]),
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28 .pin_18(IOVCC),
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29 .pin_19(VCI),
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30 .pin_20(RD),
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31 .pin_21(WR),
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32 .pin_22(RS),
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33 .pin_23(CS),
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34 .pin_24(RESET),
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35 .pin_25(IM0),
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36 .pin_26(GND),
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37 .pin_27(LEDA),
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38 .pin_28(LEDK[1]),
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39 .pin_29(LEDK[2]),
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40 .pin_30(LEDK[3]),
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41 /* the remaining pins are NC */
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42 .pin_31(),
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43 .pin_32(),
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44 .pin_33(),
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45 .pin_34(),
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46 .pin_35(),
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47 .pin_36()
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48 );
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49
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50 endmodule