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annotate duart28c/src/vsrc/FT2232D_chip.v @ 80:6bd0e0627938

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sim-fpc-pasv: starting project with MCL
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 25 Oct 2022 03:17:34 +0000
parents d80978bd645e
children
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46
d80978bd645e duart28c: started with a copy from duart28
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1 /*
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2 * This module encapsulates the FT2232D chip and its pinout.
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3 */
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4
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5 module FT2232D_chip (GND, AGND, VCC, AVCC, VCCIOA, VCCIOB, OUT_3V3,
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6 USBDP, USBDM, EECS, EESK, EEDATA, RESET, RSTOUT, TEST, PWREN,
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7 XTIN, XTOUT, ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB);
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8
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9 input GND, AGND, VCC, AVCC, VCCIOA, VCCIOB;
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10 output OUT_3V3;
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11
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12 inout USBDP, USBDM;
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13 output EECS, EESK;
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14 inout EEDATA;
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15
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16 input RESET, TEST;
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17 output RSTOUT, PWREN;
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18
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19 input XTIN;
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20 output XTOUT;
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21
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22 inout [7:0] ADBUS, BDBUS;
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23 inout [3:0] ACBUS, BCBUS;
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24 input SI_WUA, SI_WUB;
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25
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26 /* instantiate the package; the mapping of signals to pins is defined here */
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27
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28 pkg_LQFP48 pkg (.pin_1(EESK),
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29 .pin_2(EEDATA),
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30 .pin_3(VCC),
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31 .pin_4(RESET),
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32 .pin_5(RSTOUT),
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33 .pin_6(OUT_3V3),
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34 .pin_7(USBDP),
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35 .pin_8(USBDM),
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36 .pin_9(GND),
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37 .pin_10(SI_WUA),
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38 .pin_11(ACBUS[3]),
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39 .pin_12(ACBUS[2]),
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40 .pin_13(ACBUS[1]),
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41 .pin_14(VCCIOA),
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42 .pin_15(ACBUS[0]),
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43 .pin_16(ADBUS[7]),
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44 .pin_17(ADBUS[6]),
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45 .pin_18(GND),
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46 .pin_19(ADBUS[5]),
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47 .pin_20(ADBUS[4]),
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48 .pin_21(ADBUS[3]),
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49 .pin_22(ADBUS[2]),
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50 .pin_23(ADBUS[1]),
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51 .pin_24(ADBUS[0]),
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52 .pin_25(GND),
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53 .pin_26(SI_WUB),
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54 .pin_27(BCBUS[3]),
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55 .pin_28(BCBUS[2]),
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56 .pin_29(BCBUS[1]),
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57 .pin_30(BCBUS[0]),
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58 .pin_31(VCCIOB),
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59 .pin_32(BDBUS[7]),
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60 .pin_33(BDBUS[6]),
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61 .pin_34(GND),
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62 .pin_35(BDBUS[5]),
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63 .pin_36(BDBUS[4]),
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64 .pin_37(BDBUS[3]),
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65 .pin_38(BDBUS[2]),
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66 .pin_39(BDBUS[1]),
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67 .pin_40(BDBUS[0]),
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68 .pin_41(PWREN),
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69 .pin_42(VCC),
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70 .pin_43(XTIN),
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71 .pin_44(XTOUT),
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72 .pin_45(AGND),
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73 .pin_46(AVCC),
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74 .pin_47(TEST),
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75 .pin_48(EECS)
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76 );
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77
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78 endmodule