FreeCalypso > hg > fc-small-hw
changeset 46:d80978bd645e
duart28c: started with a copy from duart28
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Wed, 29 Jul 2020 07:08:28 +0000 |
parents | 2f8a4e3c48cb |
children | ba1450b0c956 |
files | duart28c/src/74LVC541APW.pinout duart28c/src/MCL duart28c/src/Makefile duart28c/src/U5.slotmap duart28c/src/U6.slotmap duart28c/src/primitives duart28c/src/sympath duart28c/src/vsrc/FT2232D_block.v duart28c/src/vsrc/FT2232D_chip.v duart28c/src/vsrc/USB_block.v duart28c/src/vsrc/application_block.v duart28c/src/vsrc/board.v duart28c/src/vsrc/eeprom_93Cx6_16bit.v duart28c/src/vsrc/regulator_ic.v duart28c/src/vsrc/regulator_with_caps.v duart28c/src/vsrc/target_if.v duart28c/src/vsrc/usb_conn.v |
diffstat | 17 files changed, 927 insertions(+), 0 deletions(-) [+] |
line wrap: on
line diff
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/74LVC541APW.pinout Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,21 @@ +#pin name pin number +nOE1 1 +A:0 2 +A:1 3 +A:2 4 +A:3 5 +A:4 6 +A:5 7 +A:6 8 +A:7 9 +GND 10 +Y:7 11 +Y:6 12 +Y:5 13 +Y:4 14 +Y:3 15 +Y:2 16 +Y:1 17 +Y:0 18 +nOE2 19 +Vcc 20
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/MCL Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,361 @@ +# Capacitors + +part tant-cap-33uF: + value=33uF + footprint=EIA6032 + description=Tantalum oxide chip capacitor, 33 uF, SMT size C + manufacturer=Kemet + manufacturer_part_number=T491C336K016AT + vendor=Digi-Key + vendor_part_number=399-3750-1-ND + npins=2 + +part 0603C-X5R-1uF: + value=1uF + footprint=0603 + description=Ceramic chip capacitor, X5R, 1 uF, 0603 + manufacturer=Taiyo Yuden + manufacturer_part_number=UMK107BJ105KA-T + vendor=Digi-Key + vendor_part_number=587-2400-1-ND + npins=2 + +part 0603C-X7R-100nF: + value=100nF + footprint=0603 + description=Ceramic chip capacitor, X7R, 0.1 uF, 0603 + manufacturer=Yageo + manufacturer_part_number=CC0603KRX7R9BB104 + vendor=Digi-Key + vendor_part_number=311-1344-1-ND + npins=2 + +part 0402C-22p: + value=22p + footprint=0402 + description=Ceramic chip capacitor, C0G, 22 pF, 0402 + manufacturer=TDK + manufacturer_part_number=C1005C0G1H220J050BA + vendor=Digi-Key + vendor_part_number=445-1239-1-ND + npins=2 + +C1: + hier=usb.VBUS_in_cap + part=0603C-X7R-100nF + +C2: + hier=usb.FT2232D.XTIN_cap + part=0402C-22p + +C3: + hier=usb.FT2232D.XTOUT_cap + part=0402C-22p + +C4: + hier=usb.P_5V_cap + part=0603C-X7R-100nF + +C5: + hier=usb.FT2232D.AVCC_cap + part=0603C-X7R-100nF + +C6: + hier=usb.FT2232D.FTDI_3V3_cap + part=0603C-X7R-100nF + +C7: + hier=usb.P_5V_cap2 + part=tant-cap-33uF + +C8: + hier=reg_3V3.input_cap + part=0603C-X5R-1uF + +C9: + hier=reg_3V3.output_cap + part=0603C-X5R-1uF + +C10: + hier=reg_2V8.input_cap + part=0603C-X5R-1uF + +C11: + hier=reg_2V8.output_cap + part=0603C-X5R-1uF + +C12: + hier=app.output_buf_bypass_cap + part=0603C-X7R-100nF + +C13: + hier=app.input_buf_bypass_cap + part=0603C-X7R-100nF + +C14: + hier=usb.FT2232D.VCCIOA_bypass_cap + part=0603C-X7R-100nF + +C15: + hier=usb.FT2232D.VCCIOB_bypass_cap + part=0603C-X7R-100nF + +# Connectors + +J1: + hier=usb.conn.conn + description=USB connector, receptacle, mini-B + manufacturer=AMP/TE + manufacturer_part_number=1734035-2 + vendor=Digi-Key + vendor_part_number=A31727CT-ND + footprint=file:USB_CONN_1734035 + npins=9 # 5 actual pins + 4 mounting pads + +# main DUART signal set +J2: + hier=app.target_if.main_if + footprint=file:HEADER10_Shrouded + description=Shrouded header, 0.100", dual row, 10 posts + manufacturer=AMP/TE + manufacturer_part_number=2-1761603-3 + vendor=Digi-Key + vendor_part_number=A97470-ND + npins=10 + +# extra header for DSR, RI and GND +J3: + hier=app.target_if.aux_if + footprint=JUMPER3 + description=Header, 0.100", single row, 3 posts + manufacturer=Molex + manufacturer_part_number=0901200123 + vendor=Digi-Key + vendor_part_number=WM8073-ND + npins=3 + +# 5V & GND bringout for misc uses +J4: + hier=aux_5V + footprint=JUMPER2 + description=Header, 0.100", 2 posts + manufacturer=Molex + manufacturer_part_number=0901200122 + vendor=Digi-Key + vendor_part_number=WM8072-ND + npins=2 + +# Ferrite bead + +L1: + hier=usb.VBUS_ferrite + manufacturer=Murata + manufacturer_part_number=BLM18AG471SN1D + description=Ferrite bead for USB, 0603 + vendor=Digi-Key + vendor_part_number=490-1013-1-ND + footprint=0603 + npins=2 + +# Resistors + +part 0402R-100k: + footprint=0402 + value=100k + description=Chip resistor, 100 kOhm, 1%, 0402 + manufacturer=Yageo + manufacturer_part_number=RC0402FR-07100KL + vendor=Digi-Key + vendor_part_number=311-100KLRCT-ND + npins=2 + +part 0402R-10k: + footprint=0402 + value=10k + description=Chip resistor, 10 kOhm, 1%, 0402 + manufacturer=Vishay Dale + manufacturer_part_number=CRCW040210K0FKED + vendor=Digi-Key + vendor_part_number=541-10.0KLCT-ND + npins=2 + +part 0402R-2k2: + footprint=0402 + value=2k2 + description=Chip resistor, 2.2 kOhm, 1%, 0402 + manufacturer=Bourns + manufacturer_part_number=CR0402-FX-2201GLF + vendor=Digi-Key + vendor_part_number=CR0402-FX-2201GLFCT-ND + npins=2 + +part 0402R-1k5: + footprint=0402 + value=1k5 + description=Chip resistor, 1.5 kOhm, 1%, 0402 + manufacturer=Yageo + manufacturer_part_number=RC0402FR-071K5L + vendor=Digi-Key + vendor_part_number=311-1.50KLRCT-ND + npins=2 + +part 0402R-470R: + footprint=0402 + value=470R + description=Chip resistor, 470 ohm, 1%, 0402 + manufacturer=Vishay Dale + manufacturer_part_number=CRCW0402470RFKEDC + vendor=Digi-Key + vendor_part_number=541-4072-1-ND + npins=2 + +part 0402R-27R: + footprint=0402 + value=27R + description=Chip resistor, 27 ohm, 1%, 0402 + manufacturer=Yageo + manufacturer_part_number=RC0402FR-0727RL + vendor=Digi-Key + vendor_part_number=YAG3086CT-ND + npins=2 + +R1: + hier=usb.FT2232D.DOUT_series_R + part=0402R-2k2 + +R2: + hier=usb.FT2232D.DOUT_pullup_R + part=0402R-10k + +R3: + hier=usb.DP_pullup_R + part=0402R-1k5 + +R4: + hier=usb.DP_series_R + part=0402R-27R + +R5: + hier=usb.DM_series_R + part=0402R-27R + +R6: + hier=usb.FT2232D.AVCC_filter_R + part=0402R-470R + +R7: + hier=app.TxD_series_R + part=0402R-2k2 + +R8: + hier=app.RTS_series_R + part=0402R-2k2 + +R9: + hier=app.DTR_series_R + part=0402R-2k2 + +R10: + hier=app.TxD2_series_R + part=0402R-2k2 + +R11: + hier=app.RxD_pullup + part=0402R-100k + +R12: + hier=app.CTS_pullup + part=0402R-100k + +R13: + hier=app.DSR_pullup + part=0402R-100k + +R14: + hier=app.DCD_pullup + part=0402R-100k + +R15: + hier=app.RI_pullup + part=0402R-100k + +R16: + hier=app.RxD2_pullup + part=0402R-100k + +# ICs + +U1: + hier=usb.FT2232D.FT2232D.pkg + manufacturer=FTDI + device=FT2232D + part=yes + description=USB to dual UART adapter IC + vendor=Digi-Key + vendor_part_number=768-1010-1-ND + footprint=LQFP48_7 + npins=48 + +U2: + hier=usb.FT2232D.eeprom.pkg + device=93C46 + manufacturer=Atmel + manufacturer_part_number=AT93C46EN-SH + description=Serial EEPROM, 64x16, SOIC-8 package + footprint=SO8 + npins=8 + +U3: + hier=reg_3V3.reg.pkg + manufacturer=TI + device=TLV70233DBV + part=yes + description=LDO regulator, 3.3 V output, SOT23-5 + vendor=Digi-Key + vendor_part_number=296-32415-1-ND + footprint=file:TLV702xxDBV + npins=5 + +U4: + hier=reg_2V8.reg.pkg + manufacturer=TI + device=TLV70228DBV + part=yes + description=LDO regulator, 2.8 V output, SOT23-5 + vendor=Digi-Key + vendor_part_number=296-39282-1-ND + footprint=file:TLV702xxDBV + npins=5 + +part 74LVC541A: + device=74LVC541A + manufacturer=Nexperia + manufacturer_part_number=74LVC541APW + description=Octal buffer IC, TSSOP20 package + vendor=Digi-Key + vendor_part_number=1727-6370-1-ND + footprint=file:TSSOP20_MNF + pinout=74LVC541APW.pinout + npins=20 + +# buffer for driving outputs from the adapter +U5: + part=74LVC541A + slotmap=U5.slotmap + +# buffer for inputs coming into the adapter +U6: + part=74LVC541A + slotmap=U6.slotmap + +# Crystal + +Y1: + hier=usb.FT2232D.xtal + manufacturer=IQD + manufacturer_part_number=LFXTAL026900 + description=Crystal, 6.0 MHz, 16 pF, HC-49 SMT + vendor=Digi-Key + vendor_part_number=1923-1509-1-ND + footprint=HC49_SMT + npins=2
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/Makefile Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,29 @@ +VSRCS= vsrc/FT2232D_block.v vsrc/FT2232D_chip.v vsrc/USB_block.v \ + vsrc/application_block.v vsrc/board.v vsrc/eeprom_93Cx6_16bit.v \ + vsrc/regulator_ic.v vsrc/regulator_with_caps.v vsrc/target_if.v \ + vsrc/usb_conn.v +BOMS= tallied-bom.txt tallied-bom.csv comptab.txt +NETS= sverp.unet bound.unet pcb-netlist.txt + +all: ${BOMS} ${NETS} + +tallied-bom.txt: MCL + ueda-mkbom -cr > $@ + +tallied-bom.csv: MCL + ueda-csvbom > $@ + +comptab.txt: MCL + ueda-shortbom > $@ + +sverp.unet: ${VSRCS} primitives Makefile + ueda-sverp -o $@ ${VSRCS} + +bound.unet: MCL sverp.unet U5.slotmap U6.slotmap + unet-bind -c sverp.unet $@ + +pcb-netlist.txt: bound.unet + unet2pcb bound.unet $@ + +clean: + rm -f *.unet *.txt *.csv errs elements.pcb
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/U5.slotmap Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,10 @@ +#instance slot +app.buf_TxD2 0 +app.buf_TxD 1 +app.buf_RTS 2 +app.buf_DTR 3 +app.unused_output_buf1 4 +app.unused_output_buf2 5 +app.unused_output_buf3 6 +app.unused_output_buf4 7 +app.output_buf_common
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/U6.slotmap Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,10 @@ +#instance slot +app.buf_RI 0 +app.buf_DCD 1 +app.buf_DSR 2 +app.buf_CTS 3 +app.buf_RxD2 4 +app.buf_RxD 5 +app.unused_input_buf1 6 +app.unused_input_buf2 7 +app.input_buf_common
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/primitives Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,27 @@ +/* + * This file defines the primitives to be instantiated from the structural + * Verilog source for the board: IC package types, basic components and + * subpackages to be mapped later in the MCL binding step. + */ + +resistor numpins 2; +capacitor numpins 2; +inductor numpins 2; + +/* IC packages */ +pkg_LQFP48 numpins 48; +pkg_5pin numpins 5; +pkg_8pin numpins 8; + +/* 74LVC541A single buffer and common part subpackages */ +buffer_ic_slot mapped_pins (A, Y); +buffer_ic_common mapped_pins (Vcc, GND, nOE1, nOE2); + +/* crystal resonator */ +xtal_2pin_pkg numpins 2; + +/* connectors */ +header_2pin numpins 2; +header_3pin numpins 3; +header_10pin numpins 10; +conn_miniUSB_plus4 numpins 9;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/sympath Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,1 @@ +.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/vsrc/FT2232D_block.v Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,90 @@ +/* + * This module encapsulates the FT2232D chip and its immediate accessories: + * the oscillator crystal, the EEPROM, the AVCC filter and the cap on 3V3OUT. + */ + +module FT2232D_block (GND, VCC, VCCIOA, VCCIOB, + USBDP, USBDM, RESET, RSTOUT, PWREN, + ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB); + +input GND, VCC, VCCIOA, VCCIOB; + +inout USBDP, USBDM; + +input RESET; +output RSTOUT, PWREN; + +inout [7:0] ADBUS, BDBUS; +inout [3:0] ACBUS, BCBUS; +input SI_WUA, SI_WUB; + +/* FT2232D pins handled within this block */ + +wire EECS, EESK, EEDATA; +wire XTIN, XTOUT; +wire AVCC, FTDI_3V3; + +/* instantiate the FT2232D */ + +FT2232D_chip FT2232D (.GND(GND), + .AGND(GND), + .VCC(VCC), + .AVCC(AVCC), + .VCCIOA(VCCIOA), + .VCCIOB(VCCIOB), + .OUT_3V3(FTDI_3V3), + .USBDP(USBDP), + .USBDM(USBDM), + .EECS(EECS), + .EESK(EESK), + .EEDATA(EEDATA), + .RESET(RESET), + .RSTOUT(RSTOUT), + .TEST(GND), + .PWREN(PWREN), + .XTIN(XTIN), + .XTOUT(XTOUT), + .ADBUS(ADBUS), + .ACBUS(ACBUS), + .SI_WUA(SI_WUA), + .BDBUS(BDBUS), + .BCBUS(BCBUS), + .SI_WUB(SI_WUB) + ); + +/* VCCIO bypass caps */ + +capacitor VCCIOA_bypass_cap (VCCIOA, GND); +capacitor VCCIOB_bypass_cap (VCCIOB, GND); + +/* AVCC filter */ + +resistor AVCC_filter_R (VCC, AVCC); +capacitor AVCC_cap (AVCC, GND); + +/* 3V3OUT */ + +capacitor FTDI_3V3_cap (FTDI_3V3, GND); + +/* crystal oscillator */ + +xtal_2pin_pkg xtal (XTIN, XTOUT); +capacitor XTIN_cap (XTIN, GND); +capacitor XTOUT_cap (XTOUT, GND); + +/* serial EEPROM */ + +wire EEPROM_DOUT; + +eeprom_93Cx6_16bit eeprom (.GND(GND), + .VCC(VCC), + .CS(EECS), + .SK(EESK), + .DIN(EEDATA), + .DOUT(EEPROM_DOUT) + ); + +resistor DOUT_series_R (EEPROM_DOUT, EEDATA); +resistor DOUT_pullup_R (EEPROM_DOUT, VCC); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/vsrc/FT2232D_chip.v Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,78 @@ +/* + * This module encapsulates the FT2232D chip and its pinout. + */ + +module FT2232D_chip (GND, AGND, VCC, AVCC, VCCIOA, VCCIOB, OUT_3V3, + USBDP, USBDM, EECS, EESK, EEDATA, RESET, RSTOUT, TEST, PWREN, + XTIN, XTOUT, ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB); + +input GND, AGND, VCC, AVCC, VCCIOA, VCCIOB; +output OUT_3V3; + +inout USBDP, USBDM; +output EECS, EESK; +inout EEDATA; + +input RESET, TEST; +output RSTOUT, PWREN; + +input XTIN; +output XTOUT; + +inout [7:0] ADBUS, BDBUS; +inout [3:0] ACBUS, BCBUS; +input SI_WUA, SI_WUB; + +/* instantiate the package; the mapping of signals to pins is defined here */ + +pkg_LQFP48 pkg (.pin_1(EESK), + .pin_2(EEDATA), + .pin_3(VCC), + .pin_4(RESET), + .pin_5(RSTOUT), + .pin_6(OUT_3V3), + .pin_7(USBDP), + .pin_8(USBDM), + .pin_9(GND), + .pin_10(SI_WUA), + .pin_11(ACBUS[3]), + .pin_12(ACBUS[2]), + .pin_13(ACBUS[1]), + .pin_14(VCCIOA), + .pin_15(ACBUS[0]), + .pin_16(ADBUS[7]), + .pin_17(ADBUS[6]), + .pin_18(GND), + .pin_19(ADBUS[5]), + .pin_20(ADBUS[4]), + .pin_21(ADBUS[3]), + .pin_22(ADBUS[2]), + .pin_23(ADBUS[1]), + .pin_24(ADBUS[0]), + .pin_25(GND), + .pin_26(SI_WUB), + .pin_27(BCBUS[3]), + .pin_28(BCBUS[2]), + .pin_29(BCBUS[1]), + .pin_30(BCBUS[0]), + .pin_31(VCCIOB), + .pin_32(BDBUS[7]), + .pin_33(BDBUS[6]), + .pin_34(GND), + .pin_35(BDBUS[5]), + .pin_36(BDBUS[4]), + .pin_37(BDBUS[3]), + .pin_38(BDBUS[2]), + .pin_39(BDBUS[1]), + .pin_40(BDBUS[0]), + .pin_41(PWREN), + .pin_42(VCC), + .pin_43(XTIN), + .pin_44(XTOUT), + .pin_45(AGND), + .pin_46(AVCC), + .pin_47(TEST), + .pin_48(EECS) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/vsrc/USB_block.v Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,67 @@ +/* + * This module encapsulates the USB connector, the FT2232D block and + * the glue components between them. + */ + +module USB_block (GND, P_5V, VCCIOA, VCCIOB, + ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB, PWREN); + +output GND, P_5V; + +input VCCIOA, VCCIOB; +inout [7:0] ADBUS, BDBUS; +inout [3:0] ACBUS, BCBUS; +input SI_WUA, SI_WUB; +output PWREN; + +/* interconnecting wires */ + +wire VBUS; +wire DM_connector_side, DM_chip_side; +wire DP_connector_side, DP_chip_side; +wire RSTOUT; + +usb_conn conn (.GND(GND), + .VBUS(VBUS), + .Dminus(DM_connector_side), + .Dplus(DP_connector_side), + .ID() /* no connect */ + ); + +/* ferrite bead on the power supply */ + +inductor VBUS_ferrite (VBUS, P_5V); + +/* series resistors on USB data lines */ + +resistor DM_series_R (DM_connector_side, DM_chip_side); +resistor DP_series_R (DP_connector_side, DP_chip_side); + +/* we can now bring in the FT2232D block */ + +FT2232D_block FT2232D (.GND(GND), + .VCC(P_5V), + .VCCIOA(VCCIOA), + .VCCIOB(VCCIOB), + .USBDP(DP_chip_side), + .USBDM(DM_chip_side), + .RESET(P_5V), + .RSTOUT(RSTOUT), + .PWREN(PWREN), + .ADBUS(ADBUS), + .ACBUS(ACBUS), + .SI_WUA(SI_WUA), + .BDBUS(BDBUS), + .BCBUS(BCBUS), + .SI_WUB(SI_WUB) + ); + +resistor DP_pullup_R (DP_chip_side, RSTOUT); + +/* power bypass caps */ + +capacitor VBUS_in_cap (VBUS, GND); +capacitor P_5V_cap (P_5V, GND); +capacitor P_5V_cap2 (P_5V, GND); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/vsrc/application_block.v Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,92 @@ +/* + * This module encapsulates the application function of our board: + * dual UART with 2.8V outputs. + */ + +module application_block (GND, P_3V3, P_2V8, ADBUS, BDBUS); + +input GND, P_3V3, P_2V8; + +inout [7:0] ADBUS, BDBUS; + +/* 2.8V output wires */ + +wire TxD_2V8_before_R, RTS_2V8_before_R, DTR_2V8_before_R, TxD2_2V8_before_R; +wire TxD_2V8_after_R, RTS_2V8_after_R, DTR_2V8_after_R, TxD2_2V8_after_R; + +/* input signal wires */ + +wire RxD_in, CTS_in, DSR_in, DCD_in, RI_in, RxD2_in; + +/* output buffers */ + +buffer_ic_common output_buf_common (.Vcc(P_2V8), + .GND(GND), + .nOE1(GND), + .nOE2(GND) + ); + +capacitor output_buf_bypass_cap (P_2V8, GND); + +buffer_ic_slot buf_TxD (.A(ADBUS[0]), .Y(TxD_2V8_before_R)); +buffer_ic_slot buf_RTS (.A(ADBUS[2]), .Y(RTS_2V8_before_R)); +buffer_ic_slot buf_DTR (.A(ADBUS[4]), .Y(DTR_2V8_before_R)); +buffer_ic_slot buf_TxD2 (.A(BDBUS[0]), .Y(TxD2_2V8_before_R)); + +buffer_ic_slot unused_output_buf1 (.A(GND), .Y()); +buffer_ic_slot unused_output_buf2 (.A(GND), .Y()); +buffer_ic_slot unused_output_buf3 (.A(GND), .Y()); +buffer_ic_slot unused_output_buf4 (.A(GND), .Y()); + +/* output series resistors */ + +resistor TxD_series_R (TxD_2V8_before_R, TxD_2V8_after_R); +resistor RTS_series_R (RTS_2V8_before_R, RTS_2V8_after_R); +resistor DTR_series_R (DTR_2V8_before_R, DTR_2V8_after_R); +resistor TxD2_series_R (TxD2_2V8_before_R, TxD2_2V8_after_R); + +/* input buffers */ + +buffer_ic_common input_buf_common (.Vcc(P_3V3), + .GND(GND), + .nOE1(GND), + .nOE2(GND) + ); + +capacitor input_buf_bypass_cap (P_3V3, GND); + +buffer_ic_slot buf_RxD (.A(RxD_in), .Y(ADBUS[1])); +buffer_ic_slot buf_CTS (.A(CTS_in), .Y(ADBUS[3])); +buffer_ic_slot buf_DSR (.A(DSR_in), .Y(ADBUS[5])); +buffer_ic_slot buf_DCD (.A(DCD_in), .Y(ADBUS[6])); +buffer_ic_slot buf_RI (.A(RI_in), .Y(ADBUS[7])); +buffer_ic_slot buf_RxD2 (.A(RxD2_in), .Y(BDBUS[1])); + +buffer_ic_slot unused_input_buf1 (.A(GND), .Y()); +buffer_ic_slot unused_input_buf2 (.A(GND), .Y()); + +/* input pull-up resistors */ + +resistor RxD_pullup (RxD_in, P_2V8); +resistor CTS_pullup (CTS_in, P_2V8); +resistor DSR_pullup (DSR_in, P_2V8); +resistor DCD_pullup (DCD_in, P_2V8); +resistor RI_pullup (RI_in, P_2V8); +resistor RxD2_pullup (RxD2_in, P_2V8); + +/* target interface headers */ + +target_if target_if ( .GND(GND), + .UART0_TxD(TxD_2V8_after_R), + .UART0_RxD(RxD_in), + .UART0_RTS(RTS_2V8_after_R), + .UART0_CTS(CTS_in), + .UART0_DTR(DTR_2V8_after_R), + .UART0_DSR(DSR_in), + .UART0_DCD(DCD_in), + .UART0_RI(RI_in), + .UART1_TxD(TxD2_2V8_after_R), + .UART1_RxD(RxD2_in) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/vsrc/board.v Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,37 @@ +module board (); + +wire GND, P_5V, P_3V3, P_2V8; + +wire [7:0] ADBUS, BDBUS; +wire [3:0] ACBUS, BCBUS; + +USB_block usb ( .GND(GND), + .P_5V(P_5V), + .VCCIOA(P_3V3), + .VCCIOB(P_3V3), + .ADBUS(ADBUS), + .ACBUS(ACBUS), + .SI_WUA(P_3V3), + .BDBUS(BDBUS), + .BCBUS(BCBUS), + .SI_WUB(P_3V3), + .PWREN() /* no connect */ + ); + +regulator_with_caps reg_3V3 (.GND(GND), .IN(P_5V), .OUT(P_3V3)); +regulator_with_caps reg_2V8 (.GND(GND), .IN(P_5V), .OUT(P_2V8)); + +application_block app ( .GND(GND), + .P_3V3(P_3V3), + .P_2V8(P_2V8), + .ADBUS(ADBUS), + .BDBUS(BDBUS) + ); + +/* auxiliary 5V output */ + +header_2pin aux_5V (.pin_1(P_5V), + .pin_2(GND) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/vsrc/eeprom_93Cx6_16bit.v Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,19 @@ +module eeprom_93Cx6_16bit (GND, VCC, CS, SK, DIN, DOUT); + +input GND, VCC; +input CS, SK, DIN; +output DOUT; + +/* instantiate the package; the mapping of signals to pins is defined here */ + +pkg_8pin pkg (.pin_1(CS), + .pin_2(SK), + .pin_3(DIN), + .pin_4(DOUT), + .pin_5(GND), + .pin_6(VCC), /* ORG input on some 93Cx6 variants */ + .pin_7(), /* no connect */ + .pin_8(VCC) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/vsrc/regulator_ic.v Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,13 @@ +module regulator_ic (IN, OUT, GND, EN); + +input IN, GND, EN; +output OUT; + +pkg_5pin pkg ( .pin_1(IN), + .pin_2(GND), + .pin_3(EN), + .pin_4(), /* no connect */ + .pin_5(OUT) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/vsrc/regulator_with_caps.v Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,15 @@ +module regulator_with_caps (GND, IN, OUT); + +input GND, IN; +output OUT; + +regulator_ic reg (.IN(IN), + .OUT(OUT), + .GND(GND), + .EN(IN) + ); + +capacitor input_cap (IN, GND); +capacitor output_cap (OUT, GND); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/vsrc/target_if.v Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,36 @@ +/* This module captures our target interfaces. */ + +module target_if (GND, UART0_TxD, UART0_RxD, UART0_RTS, UART0_CTS, + UART0_DTR, UART0_DSR, UART0_DCD, UART0_RI, + UART1_TxD, UART1_RxD); + +input GND; + +input UART0_TxD, UART0_RTS, UART0_DTR; +output UART0_RxD, UART0_CTS, UART0_DSR, UART0_DCD, UART0_RI; + +input UART1_TxD; +output UART1_RxD; + +/* main DUART signal set header */ + +header_10pin main_if ( .pin_1(GND), + .pin_2(GND), + .pin_3(UART1_RxD), + .pin_4(UART0_RxD), + .pin_5(UART1_TxD), + .pin_6(UART0_TxD), + .pin_7(UART0_DCD), + .pin_8(UART0_CTS), + .pin_9(UART0_DTR), + .pin_10(UART0_RTS) + ); + +/* auxiliary DSR and RI */ + +header_3pin aux_if (.pin_1(GND), + .pin_2(UART0_DSR), + .pin_3(UART0_RI) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/duart28c/src/vsrc/usb_conn.v Wed Jul 29 07:08:28 2020 +0000 @@ -0,0 +1,21 @@ +/* + * This module captures the mini-USB connector. + */ + +module usb_conn (GND, VBUS, Dminus, Dplus, ID); + +inout GND, VBUS, Dminus, Dplus, ID; + +conn_miniUSB_plus4 conn (.pin_1(VBUS), + .pin_2(Dminus), + .pin_3(Dplus), + .pin_4(ID), + .pin_5(GND), + /* mounting pads */ + .pin_6(GND), + .pin_7(GND), + .pin_8(GND), + .pin_9(GND) + ); + +endmodule