FreeCalypso > hg > fc-small-hw
annotate lunalcd2/src/vsrc/current_select.v @ 81:6feb6db2c0bf
sim-fpc-pasv MCL: FPC connector footprint
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Tue, 25 Oct 2022 05:13:55 +0000 |
parents | d5d14b426faa |
children |
rev | line source |
---|---|
59
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1 module current_select (Vio, SET); |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2 |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 input Vio; |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 output SET; |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 wire sw_1mA, sw_2mA, sw_4mA, sw_8mA; |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 pkg_DIP_SW_x4 dipsw ( .pin_1(Vio), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 .pin_2(sw_8mA), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 .pin_3(Vio), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 .pin_4(sw_4mA), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 .pin_5(Vio), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 .pin_6(sw_2mA), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 .pin_7(Vio), |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 .pin_8(sw_1mA) |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
16 ); |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
17 |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
18 resistor R_1mA (sw_1mA, SET); |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
19 resistor R_2mA (sw_2mA, SET); |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
20 resistor R_4mA (sw_4mA, SET); |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
21 resistor R_8mA (sw_8mA, SET); |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
22 |
d5d14b426faa
lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
23 endmodule |