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annotate duart28/src/vsrc/application_block.v @ 75:bb736a53463d

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lunalcd3.pcb: extend ground plane for top bracket addition
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 18 Nov 2021 06:45:36 +0000
parents bd7eec55ebc0
children
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1 /*
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2 * This module encapsulates the application function of our board:
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3 * dual UART with 2.8V outputs.
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4 */
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6 module application_block (GND, P_3V3, P_2V8, ADBUS, BDBUS);
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8 input GND, P_3V3, P_2V8;
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10 inout [7:0] ADBUS, BDBUS;
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12 /* 2.8V output wires */
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14 wire TxD_2V8_before_R, RTS_2V8_before_R, DTR_2V8_before_R, TxD2_2V8_before_R;
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15 wire TxD_2V8_after_R, RTS_2V8_after_R, DTR_2V8_after_R, TxD2_2V8_after_R;
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17 /* input signal wires */
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18
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19 wire RxD_in, CTS_in, DSR_in, DCD_in, RI_in, RxD2_in;
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21 /* output buffers */
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23 buffer_ic_common output_buf_common (.Vcc(P_2V8),
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24 .GND(GND),
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25 .nOE1(GND),
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26 .nOE2(GND)
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27 );
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29 capacitor output_buf_bypass_cap (P_2V8, GND);
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31 buffer_ic_slot buf_TxD (.A(ADBUS[0]), .Y(TxD_2V8_before_R));
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32 buffer_ic_slot buf_RTS (.A(ADBUS[2]), .Y(RTS_2V8_before_R));
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33 buffer_ic_slot buf_DTR (.A(ADBUS[4]), .Y(DTR_2V8_before_R));
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34 buffer_ic_slot buf_TxD2 (.A(BDBUS[0]), .Y(TxD2_2V8_before_R));
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35
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36 buffer_ic_slot unused_output_buf1 (.A(GND), .Y());
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37 buffer_ic_slot unused_output_buf2 (.A(GND), .Y());
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38 buffer_ic_slot unused_output_buf3 (.A(GND), .Y());
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39 buffer_ic_slot unused_output_buf4 (.A(GND), .Y());
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41 /* output series resistors */
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42
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43 resistor TxD_series_R (TxD_2V8_before_R, TxD_2V8_after_R);
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44 resistor RTS_series_R (RTS_2V8_before_R, RTS_2V8_after_R);
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45 resistor DTR_series_R (DTR_2V8_before_R, DTR_2V8_after_R);
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46 resistor TxD2_series_R (TxD2_2V8_before_R, TxD2_2V8_after_R);
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47
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48 /* input buffers */
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50 buffer_ic_common input_buf_common (.Vcc(P_3V3),
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51 .GND(GND),
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52 .nOE1(GND),
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53 .nOE2(GND)
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54 );
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56 capacitor input_buf_bypass_cap (P_3V3, GND);
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57
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58 buffer_ic_slot buf_RxD (.A(RxD_in), .Y(ADBUS[1]));
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59 buffer_ic_slot buf_CTS (.A(CTS_in), .Y(ADBUS[3]));
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60 buffer_ic_slot buf_DSR (.A(DSR_in), .Y(ADBUS[5]));
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61 buffer_ic_slot buf_DCD (.A(DCD_in), .Y(ADBUS[6]));
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62 buffer_ic_slot buf_RI (.A(RI_in), .Y(ADBUS[7]));
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63 buffer_ic_slot buf_RxD2 (.A(RxD2_in), .Y(BDBUS[1]));
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64
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65 buffer_ic_slot unused_input_buf1 (.A(GND), .Y());
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66 buffer_ic_slot unused_input_buf2 (.A(GND), .Y());
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67
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68 /* input pull-up resistors */
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69
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70 resistor RxD_pullup (RxD_in, P_2V8);
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71 resistor CTS_pullup (CTS_in, P_2V8);
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72 resistor DSR_pullup (DSR_in, P_2V8);
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73 resistor DCD_pullup (DCD_in, P_2V8);
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74 resistor RI_pullup (RI_in, P_2V8);
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75 resistor RxD2_pullup (RxD2_in, P_2V8);
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77 /* target interface headers */
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78
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79 target_if target_if ( .GND(GND),
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80 .UART0_TxD(TxD_2V8_after_R),
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81 .UART0_RxD(RxD_in),
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82 .UART0_RTS(RTS_2V8_after_R),
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83 .UART0_CTS(CTS_in),
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84 .UART0_DTR(DTR_2V8_after_R),
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85 .UART0_DSR(DSR_in),
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86 .UART0_DCD(DCD_in),
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87 .UART0_RI(RI_in),
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88 .UART1_TxD(TxD2_2V8_after_R),
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89 .UART1_RxD(RxD2_in)
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90 );
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91
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92 endmodule