FreeCalypso > hg > fc-small-hw
view duart28/src/vsrc/application_block.v @ 75:bb736a53463d
lunalcd3.pcb: extend ground plane for top bracket addition
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 18 Nov 2021 06:45:36 +0000 |
parents | bd7eec55ebc0 |
children |
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/* * This module encapsulates the application function of our board: * dual UART with 2.8V outputs. */ module application_block (GND, P_3V3, P_2V8, ADBUS, BDBUS); input GND, P_3V3, P_2V8; inout [7:0] ADBUS, BDBUS; /* 2.8V output wires */ wire TxD_2V8_before_R, RTS_2V8_before_R, DTR_2V8_before_R, TxD2_2V8_before_R; wire TxD_2V8_after_R, RTS_2V8_after_R, DTR_2V8_after_R, TxD2_2V8_after_R; /* input signal wires */ wire RxD_in, CTS_in, DSR_in, DCD_in, RI_in, RxD2_in; /* output buffers */ buffer_ic_common output_buf_common (.Vcc(P_2V8), .GND(GND), .nOE1(GND), .nOE2(GND) ); capacitor output_buf_bypass_cap (P_2V8, GND); buffer_ic_slot buf_TxD (.A(ADBUS[0]), .Y(TxD_2V8_before_R)); buffer_ic_slot buf_RTS (.A(ADBUS[2]), .Y(RTS_2V8_before_R)); buffer_ic_slot buf_DTR (.A(ADBUS[4]), .Y(DTR_2V8_before_R)); buffer_ic_slot buf_TxD2 (.A(BDBUS[0]), .Y(TxD2_2V8_before_R)); buffer_ic_slot unused_output_buf1 (.A(GND), .Y()); buffer_ic_slot unused_output_buf2 (.A(GND), .Y()); buffer_ic_slot unused_output_buf3 (.A(GND), .Y()); buffer_ic_slot unused_output_buf4 (.A(GND), .Y()); /* output series resistors */ resistor TxD_series_R (TxD_2V8_before_R, TxD_2V8_after_R); resistor RTS_series_R (RTS_2V8_before_R, RTS_2V8_after_R); resistor DTR_series_R (DTR_2V8_before_R, DTR_2V8_after_R); resistor TxD2_series_R (TxD2_2V8_before_R, TxD2_2V8_after_R); /* input buffers */ buffer_ic_common input_buf_common (.Vcc(P_3V3), .GND(GND), .nOE1(GND), .nOE2(GND) ); capacitor input_buf_bypass_cap (P_3V3, GND); buffer_ic_slot buf_RxD (.A(RxD_in), .Y(ADBUS[1])); buffer_ic_slot buf_CTS (.A(CTS_in), .Y(ADBUS[3])); buffer_ic_slot buf_DSR (.A(DSR_in), .Y(ADBUS[5])); buffer_ic_slot buf_DCD (.A(DCD_in), .Y(ADBUS[6])); buffer_ic_slot buf_RI (.A(RI_in), .Y(ADBUS[7])); buffer_ic_slot buf_RxD2 (.A(RxD2_in), .Y(BDBUS[1])); buffer_ic_slot unused_input_buf1 (.A(GND), .Y()); buffer_ic_slot unused_input_buf2 (.A(GND), .Y()); /* input pull-up resistors */ resistor RxD_pullup (RxD_in, P_2V8); resistor CTS_pullup (CTS_in, P_2V8); resistor DSR_pullup (DSR_in, P_2V8); resistor DCD_pullup (DCD_in, P_2V8); resistor RI_pullup (RI_in, P_2V8); resistor RxD2_pullup (RxD2_in, P_2V8); /* target interface headers */ target_if target_if ( .GND(GND), .UART0_TxD(TxD_2V8_after_R), .UART0_RxD(RxD_in), .UART0_RTS(RTS_2V8_after_R), .UART0_CTS(CTS_in), .UART0_DTR(DTR_2V8_after_R), .UART0_DSR(DSR_in), .UART0_DCD(DCD_in), .UART0_RI(RI_in), .UART1_TxD(TxD2_2V8_after_R), .UART1_RxD(RxD2_in) ); endmodule